TDA9962
12-bit, 3.0 V, up to 25 Msps analog-to-digital interface for CCD
cameras
Rev. 02 — 4 August 2000
Objective specification
1. Description
The TDA9962 is a 12-bit analog-to-digital interface for CCD cameras. The device
includes a correlated double sampling circuit, PGA, clamp loops and a low-power
12-bit ADC together with its reference voltage regulator.
The PGA gain and the ADC input clamp level are controlled via the serial interface.
An additional DAC is provided for additional system controls; its output voltage range
is 1.0 V (p-p) which is available at pin OFDOUT.
2. Features
s
Correlated Double Sampling (CDS), Programmable Gain Amplifier (PGA), 12-bit
Analog-to-Digital Converter (ADC) and reference regulator included
s
Fully programmable via a 3-wire serial interface
s
Sampling frequency up to 25 MHz (TDA9962HL = 20 MHz;
TDA9962HL/S1 = 25 MHz)
s
PGA gain range of 24 dB (in steps of 0.1 dB)
s
Low power consumption of only 125 mW at 2.7 V
s
Power consumption in standby mode of 4.5 mW (typ.)
s
3.0 V operation and 2.2 to 3.6 V operation for the digital outputs
s
All digital inputs accept 5 V signals
s
Active control pulses polarity selectable via serial interface
s
8-bit DAC included for analog settings
s
TTL compatible inputs, CMOS compatible outputs.
c
c
3. Applications
s
Low-power, low-voltage CCD camera systems.
Philips Semiconductors
TDA9962
12-bit, 3.0 V, up to 25 Msps analog-to-digital interface for CCD cameras
4. Quick reference data
Table 1:
Symbol
V
CCA
V
CCD
V
CCO
I
CCA
I
CCD
I
CCO
ADC
res
V
i(CDS)(p-p)
f
pix(max)
f
pix(min)
DR
PGA
N
tot(rms)
E
in(rms)
P
tot
Quick reference data
Parameter
analog supply voltage
digital supply voltage
digital outputs supply voltage
analog supply current
digital supply current
digital outputs supply current
ADC resolution
maximum CDS input voltage
(peak-to-peak value)
maximum pixel rate
minimum pixel rate
PGA dynamic range
total noise from CDS input to
ADC output
equivalent input noise
(RMS value)
total power consumption
PGA code = 00; see
Figure 8
PGA code = 256
V
CCA
= V
CCD
= V
CCO
= 3 V
V
CCA
= V
CCD
= V
CCO
= 2.7 V
V
CC
= 2.85 V
V
CC
≥
3.0 V
f
pix
= 20 MHz; C
L
= 20 pF; input ramp
response time is 800
µs
all clamps active
Conditions
Min
2.7
2.7
2.2
−
−
−
−
650
800
25
tbf
−
−
−
−
−
Typ
3.0
3.0
2.5
41
5.0
0.5
12
−
−
−
−
24
1.4
95
140
125
Max
3.6
3.6
3.6
−
−
−
−
−
−
−
−
−
−
−
−
−
Unit
V
V
V
mA
mA
mA
bits
mV
mV
MHz
MHz
dB
LSB
µV
mW
mW
5. Ordering information
Table 2:
Ordering information
Package
Name
TDA9962HL
TDA9962HL/S1
LQFP48
Description
Version
Pixel frequency
20 MHz
25 MHz
plastic low profile quad flat package; 48 leads; SOT313-2
body 7
×
7
×
1.4 mm
Type number
9397 750 07343
© Philips Electronics N.V. 2000. All rights reserved.
Objective specification
Rev. 02 — 4 August 2000
2 of 24
Objective specification
Rev. 02 — 4 August 2000
3 of 24
9397 750 07343
6. Block diagram
Philips Semiconductors
SHP
45
SHD
46
VCCA1
1
AGND1
2
VCCA4
41
AGND6 CLPOB CLPDM
40
44
48
BLK
CLK
OE
43
47
39
22
21
DGND1
VCCD1
OGND2
CDS CLOCK GENERATOR
37
38
36
CLAMP
CPCDS2
VCCA2
AGND2
9
7
3
CORRELATED
DOUBLE
SAMPLING
PGA
35
34
33
32
12-bit, 3.0 V, up to 25 Msps analog-to-digital interface for CCD cameras
CPCDS1
8
VCCO2
D11
D10
D9
D8
D7
4
hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh
IN
31
BLACK
DATA
D6
OUTPUT
LEVEL
FLIP-
SHIFT
hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh
30
BLANKING
BUFFER
D5
SHIFT
FLOP
29
hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh
D4
12-bit ADC
28
hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh
D3
CLAMP
27
D2
hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh
26
14
5
OFD DAC
Vref
8-BIT
REGISTER
25
D1
D0
OGND1
VCCO1
DCLPC
VCCA3
AGND3
TDA9962
7-BIT
REGISTER
24
23
OFDOUT
11
8-BIT
REGISTER
SERIAL
INTERFACE
REGULATOR
10
12
© Philips Electronics N.V. 2000. All rights reserved.
6
13
15
16
19
18
17
20
42
FCE504
TEST
AGND4
AGND5
OPGA
OPGAC
SEN
SCLK SDATA VSYNC
STDBY
TDA9962
Fig 1. Block diagram.
Philips Semiconductors
TDA9962
12-bit, 3.0 V, up to 25 Msps analog-to-digital interface for CCD cameras
7. Pinning information
7.1 Pinning
handbook, full pagewidth
VCCA1 1
AGND1 2
AGND2 3
IN 4
AGND3 5
AGND4 6
VCCA2 7
CPCDS1 8
CPCDS2 9
DCLPC 10
OFDOUT 11
TEST 12
37 OGND2
48 CLPDM
38 VCCO2
44 CLPOB
40 AGND6
42 STDBY
41 VCCA4
46 SHD
45 SHP
47 CLK
43 BLK
39 OE
36 D11
35 D10
34 D9
33 D8
32 D7
TDA9962HL
31 D6
30 D5
29 D4
28 D3
27 D2
26 D1
25 D0
AGND5 13
OPGAC 16
VSYNC 20
VCCD1 21
VCCA3 14
OPGA 15
SDATA 17
SCLK 18
SEN 19
DGND1 22
VCCO1 23
OGND1 24
FCE505
Fig 2. Pin configuration.
7.2 Pin description
Table 3:
Symbol
V
CCA1
AGND1
AGND2
IN
AGND3
AGND4
V
CCA2
CPCDS1
CPCDS2
DCLPC
OFDOUT
TEST
AGND5
V
CCA3
9397 750 07343
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
analog supply voltage 1
analog ground 1
analog ground 2
input signal from CCD
analog ground 3
analog ground 4
analog supply voltage 2
clamp storage capacitor pin 1
clamp storage capacitor pin 2
regulator decoupling pin
analog output of the additional 8-bit control DAC
test mode input pin (should be connected to AGND5)
analog ground 5
analog supply voltage 3
© Philips Electronics N.V. 2000. All rights reserved.
Objective specification
Rev. 02 — 4 August 2000
4 of 24
Philips Semiconductors
TDA9962
12-bit, 3.0 V, up to 25 Msps analog-to-digital interface for CCD cameras
Pin description
…continued
Pin
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Description
PGA output (test pin)
PGA complementary output (test pin)
serial data input for serial interface control
serial clock input for serial interface
strobe pin for serial interface
vertical sync pulse input
digital supply voltage 1
digital ground 1
digital outputs supply voltage 1
digital output ground 1
ADC digital output 0 (LSB)
ADC digital output 1
ADC digital output 2
ADC digital output 3
ADC digital output 4
ADC digital output 5
ADC digital output 6
ADC digital output 7
ADC digital output 8
ADC digital output 9
ADC digital output 10
ADC digital output 11 (MSB)
digital output ground 2
digital outputs supply voltage 2
output enable control input (LOW = outputs active;
HIGH = outputs in high-impedance)
analog ground 6
analog supply voltage 4
standby mode control input (LOW = TDA9962 active;
HIGH = TDA9962 standby)
blanking control input
clamp pulse input at optical black
preset sample-and-hold pulse input
data sample-and-hold pulse input
data clock input
clamp pulse input at dummy pixel
Table 3:
Symbol
OPGA
OPGAC
SDATA
SCLK
SEN
VSYNC
V
CCD1
DGND1
V
CCO1
OGND1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
OGND2
V
CCO2
OE
AGND6
V
CCA4
STDBY
BLK
CLPOB
SHP
SHD
CLK
CLPDM
9397 750 07343
© Philips Electronics N.V. 2000. All rights reserved.
Objective specification
Rev. 02 — 4 August 2000
5 of 24
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