74LVX125 Low Voltage Quad Buffer with 3-STATE Outputs
February 1994
Revised February 2005
74LVX125
Low Voltage Quad Buffer with 3-STATE Outputs
General Description
The LVX125 contains four independent non-inverting buff-
ers with 3-STATE outputs. The inputs tolerate voltages up
to 7V allowing the interface of 5V systems to 3V systems.
Features
s
Input voltage level translation from 5V to 3V
s
Ideal for low power/low noise 3.3V applications
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Order Number
74LVX125M
74LVX125SJ
74LVX125MTC
74LVX125MTCX_NL
(Note 1)
Package
Number
M14A
M14D
MTC14
MTC14
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1:
“_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Logic Symbol
IEEE/IEC
Connection Diagram
Truth Table
Pin Descriptions
OE
n
Pin Names
A
n
OE
n
O
n
Description
Inputs
Output Enable Inputs
Outputs
L
L
H
H HIGH Voltage Level
L LOW Voltage Level
Z High Impedance
X Immaterial
Inputs
A
n
L
H
X
Output
O
n
L
H
Z
© 2005 Fairchild Semiconductor Corporation
DS012007
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74LVX125
Absolute Maximum Ratings
(Note 2)
Supply Voltage (V
CC
)
DC Input Diode Current
(I
IK
) V
I
0.5V to
7.0V
20 mA
0.5V to
7.0V
20 mA
20 mA
0.5V to V
CC
0.5V
r
25 mA
r
50 mA
65
q
C to
150
q
C
180 mW
Recommended Operating
Conditions
(Note 3)
Supply Voltage (V
CC
)
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Input Rise and Fall Time (
'
t/
'
V)
2.0V to 3.6V
0V to 5.5V
0V to V
CC
0.5V
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
V
O
0.5V
V
CC
0.5V
40
q
C to
85
q
C
0 ns/V to 100 ns/V
Output Voltage (V
O
)
DC Output Source/Sink Current (I
O
)
DC V
CC
or Ground Current
(I
CC
or I
GND
)
Storage Temperature Range (T
STG
)
Power Dissipation
Note 2:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 3:
Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
V
IH
Parameter
HIGH Level
Input Voltage
V
IL
LOW Level
Input Voltage
V
OH
HIGH Level
Output Voltage
V
OL
LOW Level
Output Voltage
I
OZ
I
IN
I
CC
3-STATE Output
Off-State Current
Input Leakage
Current
Quiescent Supply
Current
3.6
4.0
40.0
3.6
V
CC
(V)
2.0
3.0
3.6
2.0
3.0
3.6
2.0
3.0
3.0
2.0
3.0
3.0
3.6
1.9
2.9
2.58
0.0
0.0
0.1
0.1
0.36
2.0
3.0
Min
1.5
2.0
2.4
0.5
0.8
0.8
1.9
2.9
2.48
0.1
0.1
0.44
V
V
IN
V
IL
or
V
IH
V
IN
V
OUT
V
IN
V
IN
V
IH
or V
IL
V
CC
or GND
5.5V or GND
V
CC
or GND
V
T
A
25
q
C
Typ
Max
T
A
40
q
C to
85
q
C
Min
1.5
2.0
2.4
0.5
0.8
0.8
Max
Units
Conditions
V
V
V
IN
V
IL
or
V
IH
I
OH
I
OH
I
OH
I
OL
I
OL
I
OL
50
P
A
50
P
A
4 mA
50
P
A
50
P
A
4 mA
r
0.25
r
0.1
r
2.5
r
1.0
P
A
P
A
P
A
Noise Characteristics
Symbol
V
OLP
V
OLV
V
IHD
V
ILD
(Note 4)
V
CC
(V)
3.3
3.3
3.3
3.3
T
A
Typ
0.3
25
q
C
Limit
0.8
V
V
V
V
Units
C
L
(pF)
50
50
50
50
Parameter
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
t
f
3 ns
0.3
0.8
2.0
0.8
Note 4:
Input t
r
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2
74LVX125
AC Electrical Characteristics
Symbol
t
PLH
t
PHL
Parameter
Propagation Delay Time
Data to Output
3.3
r
0.3
t
PZH
t
PZL
3.3
r
0.3
t
PHZ
t
PLZ
t
OSHL
t
OSLH
Output Disable
Time
Output to Output
Skew (Note 5)
2.7
3.3
r
0.3
2.7
3.3
|t
PLHm
t
PLHn
|, t
OSHL
V
CC
(V)
2.7
Min
T
A
25
q
C
Typ
5.8
8.3
4.4
6.9
5.3
7.8
4.0
6.5
10.0
8.3
Max
10.1
13.6
6.2
9.7
9.3
12.8
5.6
9.1
15.7
11.2
1.5
1.5
|t
PHLm
t
PHLn
|
T
A
40
q
C to
85
q
C
Min
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max
13.5
17.0
8.5
12.0
12.5
16.0
7.5
11.0
19.0
13.0
1.5
1.5
Units
C
L
ns
C
L
C
L
C
L
C
L
ns
C
L
C
L
C
L
ns
ns
C
L
C
L
C
L
Conditions
15 pF
50 pF
15 pF
50 pF
15 pF, R
L
50 pF, R
L
15 pF, R
L
50 pF, R
L
50 pF, R
L
50 pF, R
L
50 pF
1 k
:
1 k
:
1 k
:
1 k
:
1 k
:
1 k
:
Output Enable Time
2.7
Note 5:
Parameter guaranteed by design. t
OSLH
Capacitance
Symbol
C
IN
C
PD
Input Capacitance
Power Dissipation
Capacitance (Note 6)
Note 6:
C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Parameter
Min
T
A
25
q
C
Typ
4.0
14
Max
10
T
A
40
q
C to
85
q
C
Min
Max
10
Units
pF
pF
3
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74LVX125
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
www.fairchildsemi.com
4
74LVX125
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
5
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