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74LVX14M

Description
LV/LV-A/LVX/H SERIES, HEX 1-INPUT INVERT GATE, PDSO14
Categorylogic    logic   
File Size86KB,7 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Environmental Compliance
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74LVX14M Overview

LV/LV-A/LVX/H SERIES, HEX 1-INPUT INVERT GATE, PDSO14

74LVX14M Parametric

Parameter NameAttribute value
Brand NameFairchild Semiconductor
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerFairchild
Parts packaging codeSOIC
package instructionSOP, SOP14,.25
Contacts14
Manufacturer packaging code14LD,SOIC,JEDEC MS-012, .150\", NARROW BODY
Reach Compliance Codecompliant
ECCN codeEAR99
Samacsys Description74LVX14M, CMOS Hex Schmitt Trigger Inverter, LVX, 4mA 2 → 3.6 V 14-Pin SOIC
seriesLV/LV-A/LVX/H
JESD-30 codeR-PDSO-G14
JESD-609 codee3
length8.6235 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeINVERTER
Humidity sensitivity level1
Number of functions6
Number of entries1
Number of terminals14
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP14,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Prop。Delay @ Nom-Sup16 ns
propagation delay (tpd)23 ns
Certification statusNot Qualified
Schmitt triggerYES
Maximum seat height1.753 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)2.7 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width3.9 mm
Base Number Matches1
74LVX14 Low Voltage Hex Inverter with Schmitt Trigger Input
March 1993
Revised February 2005
74LVX14
Low Voltage Hex Inverter with Schmitt Trigger Input
General Description
The LVX14 contains six inverter gates each with a Schmitt
trigger input. They are capable of transforming slowly
changing input signals into sharply defined, jitter-free out-
put signals. In addition, they have a greater noise margin
than conventional inverters.
The LVX14 has hysteresis between the positive-going and
negative-going input thresholds (typically 1.0V) which is
determined internally by transistor ratios and is essentially
insensitive to temperature and supply voltage variations.
The inputs tolerate voltages up to 7V allowing the interface
of 5V systems to 3V systems.
Features
s
Input voltage level translation from 5V to 3V
s
Ideal for low power/low noise 3.3V applications
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Order Number
74LVX14M
74LVX14MX_NL
74LVX14SJ
74LVX14MTC
74LVX14MTCX_NL
(Note 1)
Package
Number
M14A
M14A
M14D
MTC14
MTC14
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1:
“_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
© 2005 Fairchild Semiconductor Corporation
DS011603
www.fairchildsemi.com

74LVX14M Related Products

74LVX14M 74LVX14MTCX 74LVX14MX 74LVX14 74LVX14SJ 74LVX14MX_NL
Description LV/LV-A/LVX/H SERIES, HEX 1-INPUT INVERT GATE, PDSO14 LV/LV-A/LVX/H SERIES, HEX 1-INPUT INVERT GATE, PDSO14 LV/LV-A/LVX/H SERIES, HEX 1-INPUT INVERT GATE, PDSO14 LV/LV-A/LVX/H SERIES, HEX 1-INPUT INVERT GATE, PDSO14 LV/LV-A/LVX/H SERIES, HEX 1-INPUT INVERT GATE, PDSO14 LV/LV-A/LVX/H SERIES, HEX 1-INPUT INVERT GATE, PDSO14
series LV/LV-A/LVX/H LV/LV-A/LVX/H LV/LV-A/LVX/H LV/LV-A/LVX/H LV/LV-A/LVX/H LV/LV-A/LVX/H
Number of functions 6 6 6 6 6 6
Number of terminals 14 14 14 14 14 14
Maximum operating temperature 85 °C 85 °C 85 °C 85 Cel 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C -40 °C -40 Cel -40 °C -40 °C
surface mount YES YES YES Yes YES YES
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal form GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING
Terminal location DUAL DUAL DUAL pair DUAL DUAL
Brand Name Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor - Fairchild Semiconductor -
Is it lead-free? Lead free Lead free Lead free - Lead free -
Is it Rohs certified? conform to conform to conform to - conform to conform to
Maker Fairchild Fairchild Fairchild - Fairchild Fairchild
Parts packaging code SOIC TSSOP SOIC - SOP SOIC
package instruction SOP, SOP14,.25 TSSOP, TSSOP14,.25 SOP, SOP14,.25 - SOP, SOP14,.3 SOP, SOP14,.25
Contacts 14 14 14 - 14 14
Manufacturer packaging code 14LD,SOIC,JEDEC MS-012, .150\", NARROW BODY 14 LD,TSSOP,JEDEC MO-153, 4.4MM WIDE 14LD,SOIC,JEDEC MS-012, .150\", NARROW BODY - 14LD,SOP,EIAJ TYPE II, 5.3MM WIDE -
Reach Compliance Code compliant compliant compliant - compliant compliant
ECCN code EAR99 EAR99 EAR99 - EAR99 -
JESD-30 code R-PDSO-G14 R-PDSO-G14 R-PDSO-G14 - R-PDSO-G14 R-PDSO-G14
JESD-609 code e3 e4 e3 - e3 e3
length 8.6235 mm 5 mm 8.6235 mm - 10.2 mm 8.6235 mm
Load capacitance (CL) 50 pF 50 pF 50 pF - 50 pF 50 pF
Logic integrated circuit type INVERTER INVERTER INVERTER - INVERTER INVERTER
Humidity sensitivity level 1 1 1 - 1 1
Number of entries 1 1 1 - 1 1
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY - PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code SOP TSSOP SOP - SOP SOP
Encapsulate equivalent code SOP14,.25 TSSOP14,.25 SOP14,.25 - SOP14,.3 SOP14,.25
Package shape RECTANGULAR RECTANGULAR RECTANGULAR - RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE - SMALL OUTLINE SMALL OUTLINE
Peak Reflow Temperature (Celsius) 260 260 260 - 260 260
power supply 3.3 V 3.3 V 3.3 V - 3.3 V 3.3 V
Prop。Delay @ Nom-Sup 16 ns 16 ns 16 ns - 16 ns 16 ns
propagation delay (tpd) 23 ns 23 ns 23 ns - 23 ns 23 ns
Certification status Not Qualified Not Qualified Not Qualified - Not Qualified Not Qualified
Schmitt trigger YES YES YES - YES YES
Maximum seat height 1.753 mm 1.2 mm 1.753 mm - 2.1 mm 1.753 mm
Maximum supply voltage (Vsup) 3.6 V 3.6 V 3.6 V - 3.6 V 3.6 V
Minimum supply voltage (Vsup) 2 V 2 V 2 V - 2 V 2 V
Nominal supply voltage (Vsup) 2.7 V 2.7 V 2.7 V - 2.7 V 2.7 V
technology CMOS CMOS CMOS - CMOS CMOS
Terminal surface Matte Tin (Sn) Nickel/Palladium/Gold (Ni/Pd/Au) Matte Tin (Sn) - Matte Tin (Sn) Matte Tin (Sn)
Terminal pitch 1.27 mm 0.65 mm 1.27 mm - 1.27 mm 1.27 mm
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED - NOT SPECIFIED NOT SPECIFIED
width 3.9 mm 4.4 mm 3.9 mm - 5.3 mm 3.9 mm
Base Number Matches 1 1 1 - 1 1
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