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74AC02SCXNLX

Description
AC SERIES, QUAD 2-INPUT NOR GATE, PDSO14
Categorysemiconductor    logic   
File Size101KB,7 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Download Datasheet Parametric View All

74AC02SCXNLX Overview

AC SERIES, QUAD 2-INPUT NOR GATE, PDSO14

74AC02SCXNLX Parametric

Parameter NameAttribute value
Number of functions4
Number of terminals14
Maximum operating temperature85 Cel
Minimum operating temperature-40 Cel
Maximum supply/operating voltage6 V
Minimum supply/operating voltage2 V
Rated supply voltage3.3 V
Processing package description0.150 INCH, MS-012, SOIC-14
Lead-freeYes
EU RoHS regulationsYes
stateACTIVE
CraftsmanshipCMOS
packaging shapeRECTANGULAR
Package SizeSMALL OUTLINE
surface mountYes
Terminal formGULL WING
Terminal spacing1.27 mm
terminal coatingMATTE TIN
Terminal locationDUAL
Packaging MaterialsPLASTIC/EPOXY
Temperature levelINDUSTRIAL
seriesAC
Logic IC typeNOR
Number of inputs2
propagation delay TPD8 ns
74AC02•74ACT02 Quad 2-Input NOR Gate
November 1988
Revised February 2005
74AC02•74ACT02
Quad 2-Input NOR Gate
General Description
The AC02/ACT02 contains four, 2-input NOR gates.
Features
s
I
CC
reduced by 50% on 74AC02 only
s
Outputs source/sink 24 mA
s
ACT02 has TTL-compatible inputs
Ordering Codes:
Order Number
74AC02SC
74AC02SCX_NL
74AC02SJ
74AC02MTC
74AC02PC
74ACT02SC
74ACT02MTC
74ACT02PC
Package
Number
M14A
M14A
M14D
MTC14
N14A
M14A
MTC14
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. (PC not available in Tape and Reel.)
Pb-Free package per JEDEC J-STD-020B.
Note 1:
“_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Pin Names
A
n
, B
n
O
n
Description
Inputs
Outputs
FACT
¥
is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS009912
www.fairchildsemi.com
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