A3977
Microstepping DMOS Driver with Translator
FEATURES AND BENEFITS
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±2.5 A, 35 V output rating
Low R
DS(on)
outputs, 0.28 Ω source, 0.22 Ω sink typical
Automatic current decay mode detection/selection
3.0 to 5.5 V logic supply voltage range
Mixed, fast, and slow current decay modes
Home output
Synchronous rectification for low power dissipation
Internal UVLO and thermal shutdown circuitry
Crossover-current protection
DESCRIPTION
The A3977 is a complete microstepping motor driver, with
built-in translator. It is designed to operate bipolar stepper
motors in full-, half-, quarter-, and eighth-step modes, with
output drive capability of 35 V and ±2.5 A. The A3977 includes
a fixed off-time current regulator that has the ability to operate in
slow-, fast-, or mixed-decay modes. This current-decay control
scheme results in reduced audible motor noise, increased step
accuracy, and reduced power dissipation.
The translator is the key to the easy implementation of the
A3977. Simply inputting one pulse on the STEP input drives the
motor one step (two logic inputs determine if it is a full-, half-,
quarter-, or eighth-step). There are no phase-sequence tables,
high-frequency control lines, or complex interfaces to program.
The A3977 interface is an ideal fit for applications where a
complex microprocessor is unavailable or over-burdened.
Internal synchronous-rectification control circuitry is provided
to improve power dissipation during PWM operation.
Internal circuit protection includes thermal shutdown with
hysteresis, undervoltage lockout (UVLO) and crossover-current
protection. Special power-up sequencing is not required.
The A3977 is supplied in a thin (<1.2 mm), 28-pin TSSOP
with an exposed thermal pad (suffix LP). The A3977 is a lead
(Pb) free, with 100% matte tin leadframe plating.
Package: 28-pin TSSOP (suffix LP) with
Exposed Thermal Pad
Not to scale
Pin-out Diagram
A3977-DS, Rev. 12
A3977
Microstepping DMOS Driver with Translator
SPECIFICATIONS
Selection Guide
Part Number
A3977SLPTR-T
Packing
4000 per reel
Package
28-pin TSSOP
Ambient Temperature, T
A
(°C)
–20 to 85
Absolute Maximum Ratings
Characteristic
Load Supply Voltage
Logic Supply Voltage
Logic Input Voltage Range
Reference Voltage
Sense Voltage (DC)
Output Current
Symbol
V
BB
V
DD
V
IN
V
REF
V
SENSE
I
OUT
Output current rating may be limited by duty cycle, ambient
temperature, and heat sinking. Under any set of conditions,
do not exceed the specified current rating or a junction
temperature of 150°C.
Range K
Range S
Pulsed, t
w
> 30 ns
Pulsed, t
w
< 30 ns
Notes
Rating
35
7.0
–0.3 to V
DD
+ 0.3
–1.0 to V
DD
+ 1
V
DD
0.5
±2.5
–40 to 125
–20 to 85
150
–55 to 150
Units
V
V
V
V
V
V
A
ºC
ºC
ºC
ºC
Operating Ambient Temperature
Maximum Junction Temperature
Storage Temperature
T
A
T
J
(max)
T
stg
Thermal Characteristics
Characteristic
Package Thermal Resistance
Symbol
R
θJA
Test Conditions*
Package LP, on 4-layer PCB based on JEDEC standard
Value
28
Units
ºC/W
*Additional thermal information available on the Allegro website.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A3977
Microstepping DMOS Driver with Translator
Pin-out Diagram and Terminal List Table
LP Package, 28-Pin TSSOP Pin-out Digram
Terminal List Table
Terminal Name
GND
SENSE1
HOME
DIR
OUT1A
NC
PFD
RC1
GND
AGND
REF
RC2
LOGIC SUPPLYNC
NC
OUT2A
MS2
MS1
SENSE2
GND
Terminal
Number
–
1
2
3
4
–
5
6
–
7*
8
9
10
–
11
12
13
14
–
Terminal Description
Analog and Power Ground
Sense Resistor for Bridge 1
Logic Output
Logic Input
DMOS H Bridge 1 Output A
No (internal) Connection
Mixed Decay Setting
Analog Input for Fixed Offtime
– Bridge 1
Analog and Power Ground
Analog Ground
Gm Reference Input
Analog Input for Fixed Offtime
– Bridge 2
VDD, the Logic Supply Voltage
No (internal) Connection
DMOS H Bridge 2 Output A
Logic Input
Logic Input
Sense Resistor for Bridge 2
Analog and Power Ground
Terminal Name
LOAD SUPPLY2
SR
RESET
OUT2B
NC
STEP
VREG
PGND
GND
VCP
CP1
CP2
NC
OUT1B
ENABLE
SLEEP
LOAD SUPPLY1
Terminal
Number
15
16
17
18
–
19
20
21*
–
22
23
24
–
25
26
27
28
Terminal Description
VBB2, the Load Supply for
Bridge 2
Logic Input
Logic Input
DMOS H Bridge 2 Output B
No (internal) Connection
Logic Input
Regulator Decoupling
Power Ground
Analog and Power Ground
Reservoir Capacitor
Charge Pump Capacitor
Charge Pump Capacitor
No (internal) Connection
DMOS H Bridge 1 Output B
Logic Input
Logic Input
VBB1, the Load Supply for
Bridge 1
*AGND and PGND on the TSSOP package must be connected together exter-
nally.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A3977
Microstepping DMOS Driver with Translator
Maximum Power Dissipation, P
D(max)
5.0
4.5
4.0
H
(R igh-
θ
J
A
Power Dissipation, P
D
(W)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
K
= PCB
28
2-
La
ºC
ye
/W
rP
)
CB
(R
wi
θ
J
t
A
=
h3
32
.8 in
2
ºC
co
/ W
pp
er
)
p
er
sid
e
20
40
60
80
100
120
Temperature (°C)
140
160
Table 1: Microstep Resolution Truth Table
MS
1
L
H
L
H
MS
2
L
L
H
H
Resolution
Full Step (2 Phase)
Half Step
Quarter Step
Eighth Step
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
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