Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic sequencer
(16
×
45
×
12)
PLS159A
DESCRIPTION
The PLS159A is a 3-State output, registered
logic element combining AND/OR gate arrays
with clocked J-K flip-flops. These J-K
flip-flops are dynamically convertible to
D-type via a “fold-back” inverting buffer and
control gate F
C
. It features 8 registered I/O
outputs (F) in conjunction with 4 bidirectional
I/O lines (B). These yield variable I/O gate
and register configurations via control gates
(D, L) ranging from 16 inputs to 12 outputs.
The AND/OR arrays consist of 32 logic AND
gates, 13 control AND gates, and 21 OR
gates with fusible link connections for
programming I/O polarity and direction. All
AND gates are linked to 4 inputs (I),
bidirectional I/O lines (B), internal flip-flop
outputs (Q), and Complement Array output
(C). The Complement Array consists of a
NOR gate optionally linked to all AND gates
for generating and propagating
complementary AND terms.
On-chip T/C buffers couple either True (I, B,
Q) or Complement (I, B, Q, C) input polarities
to all AND gates, whose outputs can be
optionally linked to all OR gates. Any of the
32 AND gates can drive bidirectional I/O lines
(B), whose output polarity is individually
programmable through a set of Ex-OR gates
for implementing AND-OR or AND-NOR logic
functions. Similarly, any of the 32 AND gates
can drive the J-K inputs of all flip-flops. There
are 4 AND gates for the Asynchronous
Preset/Reset functions.
All flip-flops are positive edge-triggered and
can be used as input, output or I/O (for
interfacing with a bidirectional data bus) in
conjunction with load control gates (L),
steering inputs (I), (B), (Q) and
programmable output select lines (E).
The PLS159A is field-programmable,
enabling the user to quickly generate custom
patterns using standard programming
equipment.
FEATURES
•
High-speed version of PLS159
•
f
MAX
= 18MHz
–
25MHz clock rate
PIN CONFIGURATIONS
N Package
CLK
I0
I1
I2
I3
B0
B1
B2
B3
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
V
CC
F7
F6
F5
F4
F3
F2
F1
F0
OE
•
Field-Programmable (Ni-Cr link)
•
4 dedicated inputs
•
13 control gates
•
32 AND gates
•
21 OR gates
•
45 product terms:
–
32 logic terms
–
13 control terms
GND 10
•
4 bidirectional I/O lines
•
8 bidirectional registers
•
J-K, T, or D-type flip-flops
•
Power-on reset feature on all flip-flops
•
Asynchronous Preset/Reset
•
Complement Array
•
Active-High or -Low outputs
•
Programmable OE control
•
Positive edge-triggered clock
•
Input loading: –100
µ
A (max.)
•
Power dissipation: 750mW (typ.)
•
TTL compatible
•
3-State outputs
APPLICATIONS
(F
n
= 1)
N = Plastic Dual In-Line Package (300mil-wide)
A Package
I1
3
I2
I3
B0
B1
B2
4
5
6
7
8
9
10
11
12
13
I0 CLK V
CC
F7
2
1 20 19
18
17
16
15
14
F6
F5
F4
F3
F2
B3 GND OE F0 F1
A = Plastic Leaded Chip Carrier
•
Random sequential logic
•
Synchronous up/down counters
•
Shift registers
•
Bidirectional data buffers
•
Timing function generators
•
System controllers/synchronizers
•
Priority encoder/registers
ORDERING INFORMATION
DESCRIPTION
20-Pin Plastic Dual In-Line Package (300mil-wide)
20-Pin Plastic Leaded Chip Carrier
ORDER CODE
PLS159AN
PLS159AA
DRAWING NUMBER
0408D
0400E
October 22, 1993
25
853–1159 11164
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic sequencer
(16
×
45
×
12)
PLS159A
FUNCTIONAL DIAGRAM
(LOGIC TERMS)
P
B
a
b
R
B
(CONTROL TERMS)
P
A
R
A
L
B
L
A
D
a
a
b
b
E
A
E
B
OE
Q
Q
C
C
S
X
P
J
M
K
(4)
CK
R
Q
B
F
P
J
M
K
(4)
R
Q
F
CK
T
31
T
0
F
C
CK
CLK
LOGIC FUNCTION
Q3
1
Q2
0
Q1
1
Q0
0
S
R
PRESENT STATE
A B C ...
S
n + 1
NEXT STATE
FLIP-FLOP TRUTH TABLE
OE
H
L
L
X
X
X
L
L
L
L
H
H
X
X
X
X
X
↑
↑
↑
↑
↑
↑
↑
↑
L
H
L
L
L
L
L
L
L
X
X
X X
L
X
X
L
L
CK
P
R J
K Q
F
Hi-Z
H
L
H
Q
H
L
Q
H*
L*
H* *
L* *
STATE REGISTER
0
0
0
1
⋅ ⋅ ⋅
X H
X
L
L
H X
L
L
L
L
SET Q
0
: J
0
= (Q
3
K
0
= 0
⋅
Q
2
Q
1
Q
0
) A B C . . .
⋅
⋅
⋅ ⋅ ⋅
L
L
L
L
H
H
+10V
L Q
H L
L H
H Q
H L
L H
H L
L H
RESET Q
1
: J
1
= 0
K
1
= (Q
3
Q
2
Q
1
Q
0
) A B C . . .
⋅
⋅
⋅
⋅ ⋅ ⋅
L H
L H
L
L
HOLD Q
2
: J
2
= 0
K
2
= 0
NOTES:
1. Positive Logic:
J-K = T
0
+ T
1
+ T
2
………………
T
31
T
n
= C⋅ (I0
⋅
I1
⋅
I2
…) ⋅
(Q
0
⋅
Q
1
…) ⋅
(B0
⋅
B1
⋅ …)
2.
↑
denotes transition from Low to High level.
3. X = Don’t care
4. * = Forced at F
n
pin for loading the J-K
flip-flop in the Input mode. The load
control term, L
n
must be enabled (HIGH)
and the p-terms that are connected to the
associated flip-flop must be forced LOW
(disabled) during Preload.
5. At P = R = H, Q = H. The final state of Q
depends on which is released first.
6. * * = Forced at F
n
pin to load J-K flip-flop
independent of program code (Diagnostic
mode), 3-State B outputs.
TOGGLE Q
3
: J
3
= (Q
3
Q
2
Q
1
Q
0
) A B C . . .
⋅ ⋅ ⋅ ⋅ ⋅ ⋅
K
3
= (Q
3
⋅
Q
2
⋅
Q
1
⋅
Q
0
)
⋅
A
⋅
B
⋅
C . . .
L H
X
L
NOTE:
Similar logic functions are applicable for D
and T mode flip-flops.
X H
October 22, 1993
27
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic sequencer
(16
×
45
×
12)
PLS159A
VIRGIN STATE
The factory shipped virgin device contains all
fusible links intact, such that:
1. OE is always enabled.
2. Preset and Reset are always disabled.
3. All transition terms are disabled.
4. All flip-flops are in D-mode unless
otherwise programmed to J-K only or J-K
or D (controlled).
5. All B pins are inputs and all F pins are
outputs unless otherwise programmed.
CAUTION: PLS159A
PROGRAMMING ALGORITHM
The programming voltage required to
program the PLS159A is higher (17.5V) than
that required to program the PLS159 (14.5V).
Consequently, the PLS159 programming
algorithm will not program the PLS159A.
Please exercise caution when accessing
programmer device codes to insure that the
correct algorithm is used.
THERMAL RATINGS
TEMPERATURE
Maximum junction
Maximum ambient
Allowable thermal rise
ambient to junction
150°C
75°C
75°C
ABSOLUTE MAXIMUM RATINGS
1
RATINGS
SYMBOL
V
CC
V
IN
V
OUT
I
IN
I
OUT
T
amb
T
stg
Supply voltage
Input voltage
Output voltage
Input currents
Output currents
Operating temperature range
Storage temperature range
0
–65
–30
PARAMETER
MIN
MAX
+7
+5.5
+5.5
+30
+100
+75
+150
UNIT
V
DC
V
DC
V
DC
mA
mA
°C
°C
NOTES:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at
these or any other condition above those indicated in the operational and programming specification of the device is not implied.
October 22, 1993
28
京公网安备 11010802033920号
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