®
74VHC08
QUAD 2-INPUT AND GATE
PRELIMINARY DATA
s
s
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 4.3 ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 2
µA
(MAX.) at T
A
= 25
o
C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 08
IMPROVED LATCH-UP IMMUNITY
LOW NOISE: V
OLP
= 0.8V (Max.)
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74VHC08M
74VHC08T
The internal circuit is composed of 2 stages
including buffer output, which provide high noise
immunity and stable output.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
DESCRIPTION
The 74VHC08 is an advanced high-speed CMOS
QUAD 2-INPUT AND GATE fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
PIN CONNECTION AND IEC LOGIC SYMBOLS
June 1999
1/7
74VHC08
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
7
14
SYMBOL
1A to 4A
1B to 4B
1Y to 4Y
GND
V
CC
NAME AND FUNCT ION
Data Inputs
Data Inputs
Data Outputs
Ground (0V)
Positive Supply Voltage
TRUTH TABLE
A
L
L
H
H
B
L
H
L
H
Y
L
L
L
H
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
T
stg
T
L
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
Storage Temperature
Lead Temperature (10 sec)
Parameter
Value
-0.5 to +7.0
-0.5 to +7.0
-0.5 to V
CC
+ 0.5
- 20
±
20
±
25
±
50
-65 to +150
300
Unit
V
V
V
mA
mA
mA
mA
o
o
I
CC
or I
GND
DC V
CC
or Ground Current
C
C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
I
V
O
T
op
dt/dv
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time (see note 1) (V
CC
= 3.3
±
0.3V)
(V
CC
= 5.0
±
0.5V)
Parameter
Valu e
2.0 to 5.5
0 to 5.5
0 to V
CC
-40 to +85
0 to 100
0 to 20
Unit
V
V
V
o
C
ns/V
ns/V
1) V
IN
from 30% to70%of V
CC
2/7
74VHC08
DC SPECIFICATIONS
Symb ol
Parameter
T est Cond ition s
V
CC
(V)
V
IH
V
IL
V
OH
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
2.0
3.0 to 5.5
2.0
3.0 to 5.5
2.0
3.0
4.5
3.0
4.5
V
OL
Low Level Output
Voltage
2.0
3.0
4.5
3.0
4.5
I
I
I
CC
Input Leakage Current
Quiescent Supply
Current
0 to 5.5
5.5
I
O
=-50
µA
I
O
=-50
µ
A
I
O
=-50
µ
A
I
O
=-4 mA
I
O
=-8 mA
I
O
=50
µA
I
O
=50
µ
A
I
O
=50
µ
A
I
O
=4 mA
I
O
=8 mA
V
I
= 5.5V or GND
V
I
= V
CC
or GND
1.9
2.9
4.4
2.58
3.94
0.0
0.0
0.0
0.1
0.1
0.1
0.36
0.36
±0.1
2
2.0
3.0
4.5
o
Value
T
A
= 25 C
Min.
1.5
0.7V
CC
0.5
0.3V
CC
1.9
2.9
4.4
2.48
3.8
0.1
0.1
0.1
0.44
0.44
±1.0
20
Typ .
Max.
-40 to 85 C
Min .
1.5
0.7V
CC
0.5
0.3V
CC
Max.
o
Un it
V
V
V
V
µA
µA
AC ELECTRICAL CHARACTERISTICS
(Input t
r
= t
f
=3 ns)
Symb ol
Parameter
Test Co ndition
V
CC
C
L
(V)
(pF )
3.3
3.3
(*)
5.0
(**)
5.0
(*) Voltage range is 3.3V
±
0.3V
(**) Voltage range is 5V
±
0.5V
(**)
(*)
Value
T
A
= 25 C
o
Un it
-40 to 85 C
Min .
1.0
1.0
1.0
1.0
Max.
10.5
14.0
7.0
9.0
o
Min.
t
PLH
t
PHL
Propagation Delay
Time
15
50
15
50
Typ .
6.2
8.7
4.3
5.8
Max.
8.8
12.3
5.9
7.9
ns
CAPACITIVE CHARACTERISTICS
Symb ol
Parameter
T est Cond ition s
o
Value
T
A
= 25 C
Min.
Typ .
4
18
Max.
10
-40 to 85 C
Min .
Max.
10
o
Un it
C
IN
C
PD
Input Capacitance
Power Dissipation
Capacitance (note 1)
pF
pF
1) C
PD
isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto
Test Circuit).Average operating current can be obtained by the following equation. I
CC
(opr) = C
PD
•
V
CC
•
f
IN
+ I
CC
/4 (per Gate)
3/7
74VHC08
DYNAMIC SWITCHING CHARACTERISTICS
Symb ol
Parameter
T est Cond ition s
V
CC
(V)
V
OLP
V
OLV
V
IHD
V
ILD
Dynamic Low Voltage
Quiet Output (note 1, 2)
Dynamic High Voltage
Input (note 1, 3)
Dynamic Low Voltage
Input (note 1, 3)
5.0
-0.8
5.0
5.0
C
L
= 50 pF
3.5
1.5
o
Value
T
A
= 25 C
Min.
Typ .
0.3
-0.3
Max.
0.8
-40 to 85 C
Min .
Max.
o
Un it
V
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 5.0V, (n -1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to5.0V. Inputs under test switching: 5.0V to threshold (V
ILD
), 0V to threshold (V
IHD
), f=1MHz.
TEST CIRCUIT
C
L
= 15/50 pF or equivalent (includes jig and probe capacitance)
R
T
= Z
OUT
of pulse generator (typically 50Ω)
WAVEFORM: PROPAGATION DELAYS
(f=1MHz; 50% duty cycle)
4/7
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