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UPD70F3033AYGC-8EU

Description
Microcontroller, 32-Bit, FLASH, 20MHz, MOS, PQFP100, 14 X 14 MM, PLASTIC, LQFP-100
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size634KB,52 Pages
ManufacturerNEC Electronics
Download Datasheet Parametric View All

UPD70F3033AYGC-8EU Overview

Microcontroller, 32-Bit, FLASH, 20MHz, MOS, PQFP100, 14 X 14 MM, PLASTIC, LQFP-100

UPD70F3033AYGC-8EU Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
package instruction14 X 14 MM, PLASTIC, LQFP-100
Reach Compliance Codecompliant
Has ADCYES
Address bus width22
bit size32
maximum clock frequency20 MHz
DAC channelNO
DMA channelYES
External data bus width16
JESD-30 codeS-PQFP-G100
JESD-609 codee0
length14 mm
Number of I/O lines83
Number of terminals100
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
PWM channelNO
Package body materialPLASTIC/EPOXY
encapsulated codeLFQFP
Package shapeSQUARE
Package formFLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
ROM programmabilityFLASH
Maximum seat height1.6 mm
speed20 MHz
Maximum supply voltage5.5 V
Minimum supply voltage4 V
Nominal supply voltage5 V
surface mountYES
technologyMOS
Temperature levelINDUSTRIAL
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width14 mm
uPs/uCs/peripheral integrated circuit typeMICROCONTROLLER
Base Number Matches1
DATA SHEET
µ
PD703031A, 703031AY, 703033A,
703033AY, 70F3033A, 70F3033AY
V850/SB1
32-BIT SINGLE-CHIP MICROCONTROLLERS
TM
MOS INTEGRATED CIRCUIT
DESCRIPTION
The
µ
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, and 70F3033AY (V850/SB1) are 32-bit single-
chip microcontrollers of the V850 Series
TM
for AV equipment.
32-bit CPU, ROM, RAM, timer/counters, serial
interfaces, A/D converter, DMA controller, and so on are integrated on a single chip.
The
µ
PD70F3033A and 70F3033AY have flash memory in place of the internal mask ROM of the
µ
PD703033A
and 703033AY. Because flash memory allows the program to be written and erased electrically with the device
mounted on the board, these products are ideal for the evaluation stages of system development, small-scale
production, and rapid development of new products.
The
µ
PD703032A, 703032AY, 70F3032A, 70F3032AY, products with a different ROM/RAM size are also
available.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
TM
V850/SB1, V850/SB2 Hardware User’s Manual: U13850E
V850 Series Architecture User’s Manual:
U10243E
FEATURES
Number of instructions: 74
Minimum instruction execution time: 50 ns (@ internal 20 MHz operation)
General-purpose registers: 32 bits
×
32 registers
Instruction set: Signed multiplication, saturation operations, 32-bit shift instructions, bit manipulation instructions,
load/store instructions
Memory space: 16 MB linear address space
Internal memory ROM: 128 KB (
µ
PD703031A, 703031AY: mask ROM)
256 KB (
µ
PD703033A, 703033AY: mask ROM)
256 KB (
µ
PD70F3033A, 70F3033AY: flash memory)
RAM: 12 KB (
µ
PD703031A, 703031AY)
16 KB (
µ
PD703033A, 703033AY, 70F3033A, 70F3033AY)
Interrupt/exception:
µ
PD703031A, 703033A, 70F3033A (external: 8, internal: 31 sources, exception: 1 source)
µ
PD703031AY, 703033AY, 70F3033AY (external: 8, internal: 32 sources, exception: 1 source)
I/O lines Total: 83
Timer/counters: 16-bit timer (2 channels: TM0, TM1)
8-bit timer (6 channels: TM2 to TM7)
Watch timer: 1 channel
Watchdog timer: 1 channel
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U14734EJ3V0DS00 (3rd edition)
Date Published January 2002 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
2000
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