TS87C54X2-MCA datasheet, PDF - EEWORLD Datasheet

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TS87C54X2-MCA: DescriptionMicrocontroller, 8-Bit, OTPROM, 40MHz, CMOS, PDIP40, PLASTIC, DIP-40; CategoryThe embedded processor and controller Microcontrollers and processors; File Size724KB，58 Pages; ManufacturerTEMIC; Websitehttp://www.temic.de/

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TS87C54X2-MCA Overview

Microcontroller, 8-Bit, OTPROM, 40MHz, CMOS, PDIP40, PLASTIC, DIP-40

TS87C54X2-MCA Parametric

Parameter Name	Attribute value
Maker	TEMIC
package instruction	PLASTIC, DIP-40
Reach Compliance Code	unknown
Has ADC	NO
Address bus width	16
bit size	8
maximum clock frequency	40 MHz
DAC channel	NO
DMA channel	NO
External data bus width	8
JESD-30 code	R-PDIP-T40
Number of I/O lines	32
Number of terminals	40
Maximum operating temperature	70 °C
Minimum operating temperature
PWM channel	NO
Package body material	PLASTIC/EPOXY
Package shape	RECTANGULAR
Package form	IN-LINE
Certification status	Not Qualified
ROM programmability	OTPROM
speed	40 MHz
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	THROUGH-HOLE
Terminal location	DUAL
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER
Base Number Matches	1

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TS80C54X2/C58X2

TS87C54X2/C58X2

8-bit CMOS Microcontroller 0-60 MHz

1. Description

TEMIC TS80C54/58X2 is high performance CMOS

ROM, OTP and EPROM versions of the 80C51 CMOS

single chip 8-bit microcontroller.

The TS80C54/58X2 retains all features of the TEMIC

80C51 with extended ROM/EPROM capacity (16/32

Kbytes), 256 bytes of internal RAM, a 6-source , 4-level

interrupt system, an on-chip oscilator and three timer/

counters.

In addition, the TS80C54/58X2 has a Hardware

Watchdog Timer, a more versatile serial channel that

facilitates multiprocessor communication (EUART) and

a X2 speed improvement mechanism.

The fully static design of the TS80C54/58X2 allows to

reduce system power consumption by bringing the clock

frequency down to any value, even DC, without loss of

data.

The TS80C54/58X2 has 2 software-selectable modes of

reduced activity for further reduction in power

consumption. In the idle mode the CPU is frozen while

the timers, the serial port and the interrupt system are still

operating. In the power-down mode the RAM is saved

and all other functions are inoperative.

2. Features

80C52 Compatible

•

8051 pin and instruction compatible

•

Four 8-bit I/O ports

•

Three 16-bit timer/counters

•

256 bytes scratchpad RAM

Interrupt Structure with

•

6 Interrupt sources

•

4 level priority interrupt system

Full duplex Enhanced UART

•

Framing error detection

•

Automatic address recognition

High-Speed Architecture

•

40 MHz @ 5V, 30MHz @ 3V

•

X2 Speed Improvement capability (6 clocks/

machine cycle)

30 MHz @ 5V, 20 MHz @ 3V (Equivalent to

60 MHz @ 5V, 40 MHz @ 3V)

Low EMI (inhibit ALE)

Power Control modes

•

Idle mode

•

Power-down mode

•

Power-off Flag

Dual Data Pointer

On-chip ROM/EPROM (16K-bytes, 32K-bytes)

Programmable Clock Out and Up/Down Timer/

Counter 2

Hardware Watchdog Timer (One-time enabled with

Reset-Out)

Asynchronous port reset

Once mode (On-chip Emulation)

Power supply: 4.5-5.5V, 2.7-5.5V

Temperature ranges: Commercial (0 to 70

C) and

Industrial (-40 to 85

Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP44

F1, CQPJ44 (window), CDIL40 (window)

Rev. B - Aug. 31, 1999

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