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ZNBG2001X10TA

Description
Analog Circuit, 1 Func, PDSO10, MSOP-10
CategoryAnalog mixed-signal IC    The signal circuit   
File Size515KB,7 Pages
ManufacturerZetex Semiconductors
Websitehttp://www.zetex.com/
Download Datasheet Parametric Compare View All

ZNBG2001X10TA Overview

Analog Circuit, 1 Func, PDSO10, MSOP-10

ZNBG2001X10TA Parametric

Parameter NameAttribute value
MakerZetex Semiconductors
package instructionTSSOP,
Reach Compliance Codeunknown
Analog Integrated Circuits - Other TypesANALOG CIRCUIT
JESD-30 codeS-PDSO-G10
JESD-609 codee3
length3 mm
Humidity sensitivity level1
Number of functions1
Number of terminals10
Maximum operating temperature80 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeSQUARE
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum seat height1.1 mm
Maximum supply voltage (Vsup)12 V
Minimum supply voltage (Vsup)5 V
surface mountYES
Temperature levelOTHER
Terminal surfaceMATTE TIN
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL
Maximum time at peak reflow temperature40
width3 mm
Base Number Matches1
ZNBG2000
ZNBG2001
FET BIAS CONTROLLER
DEVICE DESCRIPTION
The ZNBG series of devices are designed to meet the
bias requirements of GaAs and HEMT FETs
commonly used in satellite receiver LNBs, PMR,
cellular telephones etc. with a minimum of external
components.
With the addition of two capacitors and a resistor the
devices provide drain voltage and current control for
2 external grounded source FETs, generating the
regulated negative rail required for FET gate biasing
whilst operating from a single supply. This negative
bias, at -3 volts, can also be used to supply other
external circuits.
The ZNBG2000/1 contains two bias stages. A single
resistor allows FET drain current to be set to the
desired level. The series also offers the choice of
drain voltage to be set for the FETs, the ZNBG2000
gives 2.2 volts drain whilst the ZNBG2001 gives 2
volts.
These devices are unconditionally stable over the full
working temperature with the FETs in place, subject
to the inclusion of the recommended gate and drain
capacitors. These ensure RF stability and minimal
injected noise.
It is possible to use less than the devices full
complement of FET bias controls, unused drain and
gate connections can be left open circuit without
affecting operation of the remaining bias circuits.
In order to protect the external FETs the circuits have
been designed to ensure that, under any conditions
including power up/down transients, the gate drive
from the bias circuits cannot exceed the range -3.5V
to 0.7V. Furthermore if the negative rail experiences a
fault condition, such as overload or short circuit, the
drain supply to the FETs will shut down avoiding
excessive current flow.
The ZNBG2000/1 are available in MSOP10 packages
for the minimum in devices size. Device operating
temperature is -40 to 80°C to suit a wide range of
environmental conditions.
FEATURES
Provides bias for GaAs and HEMT FETs
Drives up to two FETs
Dynamic FET protection
Drain current set by external resistor
Regulated negative rail generator requires only 2
external capacitors
APPLICATIONS
Satellite receiver LNBs
Private mobile radio (PMR)
Single in single out C Band LNB
Cellular telephones
Choice in drain voltage
Wide supply voltage range
MSOP surface mount package
ISSUE 1 - AUGUST 2001
1

ZNBG2001X10TA Related Products

ZNBG2001X10TA ZNBG2001X10TC
Description Analog Circuit, 1 Func, PDSO10, MSOP-10 Analog Circuit, 1 Func, PDSO10, MSOP-10
Maker Zetex Semiconductors Zetex Semiconductors
package instruction TSSOP, TSSOP,
Reach Compliance Code unknown unknow
Analog Integrated Circuits - Other Types ANALOG CIRCUIT ANALOG CIRCUIT
JESD-30 code S-PDSO-G10 S-PDSO-G10
JESD-609 code e3 e3
length 3 mm 3 mm
Humidity sensitivity level 1 1
Number of functions 1 1
Number of terminals 10 10
Maximum operating temperature 80 °C 80 °C
Minimum operating temperature -40 °C -40 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP TSSOP
Package shape SQUARE SQUARE
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius) 260 260
Certification status Not Qualified Not Qualified
Maximum seat height 1.1 mm 1.1 mm
Maximum supply voltage (Vsup) 12 V 12 V
Minimum supply voltage (Vsup) 5 V 5 V
surface mount YES YES
Temperature level OTHER OTHER
Terminal surface MATTE TIN MATTE TIN
Terminal form GULL WING GULL WING
Terminal pitch 0.5 mm 0.5 mm
Terminal location DUAL DUAL
Maximum time at peak reflow temperature 40 40
width 3 mm 3 mm
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