74LV27PW-T datasheet, PDF - EEWORLD Datasheet

74LV27PW-T: DescriptionNOR Gate, CMOS, PDSO14,; Categorylogic logic; File Size359KB，8 Pages; ManufacturerPhilips Semiconductors (NXP Semiconductors N.V.); Websitehttps://www.nxp.com/

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74LV27PW-T Overview

NOR Gate, CMOS, PDSO14,

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Philips Semiconductors (NXP Semiconductors N.V.)
package instruction	TSSOP, TSSOP14,.25
Reach Compliance Code	unknown
JESD-30 code	R-PDSO-G14
JESD-609 code	e0
Load capacitance (CL)	50 pF
Logic integrated circuit type	NOR GATE
MaximumI(ol)	0.016 A
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP14,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing	TAPE AND REEL
power supply	3.3 V
Prop。Delay @ Nom-Sup	16 ns
Certification status	Not Qualified
Schmitt trigger	NO
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.635 mm
Terminal location	DUAL
Base Number Matches	1

	74LV27PW-T	74LV27DB-T
Description	NOR Gate, CMOS, PDSO14,	NOR Gate, CMOS, PDSO14,
Is it Rohs certified?	incompatible	incompatible
Maker	Philips Semiconductors (NXP Semiconductors N.V.)	Philips Semiconductors (NXP Semiconductors N.V.)
package instruction	TSSOP, TSSOP14,.25	SSOP, SSOP14,.3
Reach Compliance Code	unknown	unknown
JESD-30 code	R-PDSO-G14	R-PDSO-G14
JESD-609 code	e0	e0
Load capacitance (CL)	50 pF	50 pF
Logic integrated circuit type	NOR GATE	NOR GATE
MaximumI(ol)	0.016 A	0.016 A
Number of terminals	14	14
Maximum operating temperature	125 °C	125 °C
Minimum operating temperature	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	SSOP
Encapsulate equivalent code	TSSOP14,.25	SSOP14,.3
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH
method of packing	TAPE AND REEL	TAPE AND REEL
power supply	3.3 V	3.3 V
Prop。Delay @ Nom-Sup	16 ns	16 ns
Certification status	Not Qualified	Not Qualified
Schmitt trigger	NO	NO
Nominal supply voltage (Vsup)	3.3 V	3.3 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	AUTOMOTIVE	AUTOMOTIVE
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	GULL WING
Terminal pitch	0.635 mm	0.635 mm
Terminal location	DUAL	DUAL
Base Number Matches	1	1

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