80960CA-33, -25, -16
32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR
• Two Instructions/Clock Sustained Execution
• Four 59 Mbytes/s DMA Channels with Data Chaining
• Demultiplexed 32-bit Burst Bus with Pipelining
s
32-bit Parallel Architecture
s
Four On-Chip DMA Channels
s
s
s
s
— Two Instructions/clock Execution
— Load/Store Architecture
— Sixteen 32-bit Global Registers
— Sixteen 32-bit Local Registers
— Manipulates 64-bit Bit Fields
— 11 Addressing Modes
— Full Parallel Fault Model
— Supervisor Protection Model
Fast Procedure Call/Return Model
— Full Procedure Call in 4 Clocks
On-Chip Register Cache
— Caches Registers on Call/Ret
— Minimum of 6 Frames Provided
— Up to 15 Programmable Frames
On-Chip Instruction Cache
— 1 Kbyte Two-Way Set Associative
— 128-bit Path to Instruction Sequencer
— Cache-Lock Modes
— Cache-Off Mode
High Bandwidth On-Chip Data RAM
— 1 Kbyte On-Chip Data RAM
— Sustains 128 bits per Clock Access
— 59 Mbytes/s Fly-by Transfers
— 32 Mbytes/s Two-Cycle Transfers
— Data Chaining
— Data Packing/Unpacking
— Programmable Priority Method
s
32-Bit Demultiplexed Burst Bus
— 128-bit Internal Data Paths to
and
from Registers
— Burst Bus for DRAM Interfacing
— Address Pipelining Option
— Fully Programmable Wait States
— Supports 8-, 16- or 32-bit Bus Widths
— Supports Unaligned Accesses
— Supervisor Protection Pin
s
Selectable Big or Little Endian Byte
Ordering
s
High-Speed Interrupt Controller
—
—
—
—
—
—
Up to 248 External Interrupts
32 Fully Programmable Priorities
Multi-mode 8-bit Interrupt Port
Four Internal DMA Interrupts
Separate, Non-maskable Interrupt Pin
Context Switch in 750 ns Typical
Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent
licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.
© INTEL CORPORATION, 1993
November 1993
Order Number: 270727-006
80960CA-33, -25, -16
32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR
CONTENTS
PAGE
1.0 PURPOSE
.................................................................................................................................................. 1
2.0 80960CA OVERVIEW.................................................................................................................................
1
2.1 The C-Series Core ..............................................................................................................................2
2.2 Pipelined, Burst Bus ...........................................................................................................................2
2.3 Flexible DMA Controller ......................................................................................................................2
2.4 Priority Interrupt Controller ..................................................................................................................2
2.5 Instruction Set Summary ....................................................................................................................3
3.0 PACKAGE INFORMATION.........................................................................................................................4
3.1 Package Introduction ..........................................................................................................................4
3.2 Pin Descriptions .................................................................................................................................. 4
3.3 80960CA Mechanical Data ............................................................................................................... 11
3.3.1 80960CA PGA Pinout ............................................................................................................ 11
3.3.2 80960CA PQFP Pinout .......................................................................................................... 15
3.4 Package Thermal Specifications ...................................................................................................... 18
3.5 Stepping Register Information .......................................................................................................... 20
3.6 Suggested Sources for 80960CA Accessories.................................................................................. 20
4.0 ELECTRICAL SPECIFICATIONS.............................................................................................................
21
4.1 Absolute Maximum Ratings .............................................................................................................. 21
4.2 Operating Conditions ........................................................................................................................ 21
4.3 Recommended Connections ............................................................................................................ 21
4.4 DC Specifications ............................................................................................................................. 22
4.5 AC Specifications .............................................................................................................................. 23
4.5.1 AC Test Conditions ................................................................................................................ 29
4.5.2 AC Timing Waveforms ........................................................................................................... 29
4.5.3 Derating Curves ..................................................................................................................... 33
5.0 RESET, BACKOFF AND HOLD ACKNOWLEDGE
................................................................................. 35
6.0 BUS WAVEFORMS
................................................................................................................................. 36
7.0 REVISION HISTORY
................................................................................................................................ 64
ii
CONTENTS
LIST OF FIGURES
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Figure 36
Figure 37
Figure 38
PAGE
80960CA Block Diagram .............................................................................................................. 1
80960CA PGA Pinout—View from Top (Pins Facing Down) ...................................................... 13
80960CA PGA Pinout —View from Bottom (Pins Facing Up) .................................................... 14
80960CA PQFP Pinout (View from Top Side) ............................................................................ 17
Measuring 80960CA PGA and PQFP Case Temperature .......................................................... 18
Register g0 ................................................................................................................................. 20
AC Test Load .............................................................................................................................. 29
Input and Output Clocks Waveform ............................................................................................ 29
CLKIN Waveform ........................................................................................................................ 29
Output Delay and Float Waveform ............................................................................................. 30
Input Setup and Hold Waveform ................................................................................................ 30
NMI, XINT7:0 Input Setup and Hold Waveform .......................................................................... 31
Hold Acknowledge Timings ........................................................................................................ 31
Bus Backoff (BOFF) Timings ...................................................................................................... 32
Relative Timings Waveforms ...................................................................................................... 33
Output Delay or Hold vs. Load Capacitance .............................................................................. 33
Rise and Fall Time Derating at Highest Operating Temperature and Minimum V
CC
.................. 34
I
CC
vs. Frequency and Temperature ........................................................................................... 34
Cold Reset Waveform ................................................................................................................ 36
Warm Reset Waveform .............................................................................................................. 37
Entering the ONCE State ........................................................................................................... 38
Clock Synchronization in the 2-x Clock Mode ............................................................................ 39
Clock Synchronization in the 1-x Clock Mode ............................................................................ 39
Non-Burst, Non-Pipelined Requests Without Wait States .......................................................... 40
Non-Burst, Non-Pipelined Read Request With Wait States ....................................................... 41
Non-Burst, Non-Pipelined Write Request With Wait States ....................................................... 42
Burst, Non-Pipelined Read Request Without Wait States, 32-Bit Bus ........................................ 43
Burst, Non-Pipelined Read Request With Wait States, 32-Bit Bus ............................................. 44
Burst, Non-Pipelined Write Request Without Wait States, 32-Bit Bus ....................................... 45
Burst, Non-Pipelined Write Request With Wait States, 32-Bit Bus ............................................. 46
Burst, Non-Pipelined Read Request With Wait States, 16-Bit Bus ............................................ 47
Burst, Non-Pipelined Read Request With Wait States, 8-Bit Bus ............................................... 48
Non-Burst, Pipelined Read Request Without Wait States, 32-Bit Bus ....................................... 49
Non-Burst, Pipelined Read Request With Wait States, 32-Bit Bus ............................................ 50
Burst, Pipelined Read Request Without Wait States, 32-Bit Bus ............................................... 51
Burst, Pipelined Read Request With Wait States, 32-Bit Bus ..................................................... 52
Burst, Pipelined Read Request With Wait States, 16-Bit Bus ..................................................... 53
Burst, Pipelined Read Request With Wait States, 8-Bit Bus ....................................................... 54
iii
CONTENTS
LIST OF FIGURES
(continued)
Figure 39
Figure 40
Figure 41
Figure 42
Figure 43
Figure 44
Figure 45
Figure 46
Figure 47
Figure 48
Figure 49
PAGE
Using External READY ............................................................................................................... 55
Terminating a Burst with BTERM ............................................................................................... 56
BOFF Functional Timing ............................................................................................................ 57
HOLD Functional Timing ............................................................................................................ 58
DREQ and DACK Functional Timing .......................................................................................... 59
EOP Functional Timing .............................................................................................................. 59
Terminal Count Functional Timing .............................................................................................. 60
FAIL Functional Timing ............................................................................................................... 60
A Summary of Aligned and Unaligned Transfers for Little Endian Regions ................................ 61
A Summary of Aligned and Unaligned Transfers for Little Endian Regions (Continued) ............ 62
Idle Bus Operation ...................................................................................................................... 63
LIST OF TABLES
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
80960CA Instruction Set .............................................................................................................. 3
Pin Description Nomenclature ...................................................................................................... 4
80960CA Pin Description — External Bus Signals ...................................................................... 5
80960CA Pin Description — Processor Control Signals .............................................................. 8
80960CA Pin Description — DMA and Interrupt Unit Control Signals ....................................... 10
80960CA PGA Pinout — In Signal Order ................................................................................... 11
80960CA PGA Pinout — In Pin Order ........................................................................................ 12
80960CA PQFP Pinout — In Signal Order ................................................................................. 15
80960CA PQFP Pinout — In Pin Order ..................................................................................... 16
Maximum T
A
at Various Airflows in
o
C (PGA Package Only) ..................................................... 18
80960CA PGA Package Thermal Characteristics ...................................................................... 19
80960CA PQFP Package Thermal Characteristics .................................................................... 19
Die Stepping Cross Reference ................................................................................................... 20
Operating Conditions (80960CA-33, -25, -16) ............................................................................ 21
DC Characteristics ..................................................................................................................... 22
80960CA AC Characteristics (33 MHz) ...................................................................................... 23
80960CA AC Characteristics (25 MHz) ...................................................................................... 25
80960CA AC Characteristics (16 MHz) ...................................................................................... 27
Reset Conditions ........................................................................................................................ 35
Hold Acknowledge and Backoff Conditions ................................................................................ 35
iv
80960CA-33, -25, -16
1.0
PURPOSE
This document provides electrical characteristics for
the 33, 25 and 16 MHz versions of the 80960CA. For
a detailed description of any 80960CA functional
topic—other than parametric performance—consult
the
80960CA Product Overview
(Order No. 270669)
or the
i960
®
CA Microprocessor User’s Manual
(Order No. 270710). To obtain data sheet updates
and errata, please call Intel’s FaxBACK
®
data-on-
demand system (1-800-628-2283 or 916-356-3105).
Other information can be obtained from Intel’s tech-
nical BBS (916-356-3600).
A 32-bit demultiplexed and pipelined burst bus
provides a 132 Mbyte/s bandwidth to a system’s
high-speed external memory sub-system. In
addition, the 80960CA’s on-chip caching of instruc-
tions, procedure context and critical program data
substantially decouple system performance from the
wait states associated with accesses to the system’s
slower, cost sensitive, main memory subsystem.
The 80960CA bus controller integrates full wait state
and bus width control for highest system perfor-
mance with minimal system design complexity.
Unaligned access and Big Endian byte order support
reduces the cost of porting existing applications to
the 80960CA.
The processor also integrates four complete data-
chaining DMA channels and a high-speed interrupt
controller on-chip. DMA channels perform: single-
cycle or two-cycle transfers, data packing and
unpacking and data chaining. Block transfers—in
addition to source or destination synchronized trans-
fers—are provided.
The interrupt controller provides full programmability
of 248 interrupt sources into 32 priority levels with a
typical interrupt task switch (”latency”) time of
750 ns.
2.0
80960CA OVERVIEW
The 80960CA is the second-generation member of
the 80960 family of embedded processors. The
80960CA is object code compatible with the 32-bit
80960 Core Architecture while including Special
Function Register extensions to control on-chip
peripherals and instruction set extensions to shift 64-
bit operands and configure on-chip hardware.
Multiple 128-bit internal buses, on-chip instruction
caching and a sophisticated instruction scheduler
allow the processor to sustain execution of two
instructions every clock and peak at execution of
three instructions per clock.
Instruction Prefetch Queue
Instruction Cache
(1 KByte, Two-way
Set Associative)
128-BIT CACHE BUS
Interrupt
Programmable
Port Interrupt Controller
Multiply/Divide
Unit
Execution
Unit
Register-side
Machine Bus
Memory-side
Machine Bus
Parallel
Instruction
Scheduler
Four-Channel
DMA Controller
Memory Region
Configuration
Bus
Controller
Bus Request
Queues
1 KByte
Data RAM
5 to 15 Sets
Register Cache
DMA
Port
Control
Address
Data
Six-port
Register File
64-Bit
SRC1 Bus
64-Bit
SRC2 Bus
64-Bit
DST Bus
32-Bit
Base Bus
128-Bit
Load Bus
128-Bit
Store Bus
Address
Generation Unit
F_CX001A
Figure 1. 80960CA Block Diagram
1
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