A
PRELIMINARY
80960CF-40, -33, -25, -16
32-BIT HIGH-PERFORMANCE SUPERSCALAR
EMBEDDED MICROPROCESSOR
• Socket and Object Code Compatible with 80960CA
• Two Instructions/Clock Sustained Execution
• Four 71 Mbytes/s DMA Channels with Data Chaining
• Demultiplexed 32-Bit Burst Bus with Pipelining
32-Bit Parallel Architecture
s
Four On-Chip DMA Channels
— Two Instructions/clock Execution
— 71 Mbytes/s Fly-by Transfers
— Load/Store Architecture
— 40 Mbytes/s Two-Cycle Transfers
— Sixteen 32-Bit Global Registers
— Data Chaining
— Sixteen 32-Bit Local Registers
— Data Packing/Unpacking
— Manipulates 64-Bit Bit Fields
— Programmable Priority Method
— 11 Addressing Modes
s
32-Bit Demultiplexed Burst Bus
— Full Parallel Fault Model
— 128-Bit Internal Data Paths to
and
from
— Supervisor Protection Model
Registers
Fast Procedure Call/Return Model
— Burst Bus for DRAM Interfacing
— Address Pipelining Option
— Full Procedure Call in 4 Clocks
— Fully Programmable Wait States
On-Chip Register Cache
— Supports 8-, 16- or 32-Bit Bus Widths
— Caches Registers on Call/Ret
— Supports Unaligned Accesses
— Minimum of 6 Frames Provided
— Supervisor Protection Pin
— Up to 15 Programmable Frames
s
High-Speed Interrupt Controller
On-Chip Instruction Cache
— Up to 248 External Interrupts
— 4 Kbyte Two-Way Set Associative
— 32 Fully Programmable Priorities
— 128-Bit Path to Instruction Sequencer
— Multi-mode 8-Bit Interrupt Port
— Cache-Lock Modes
— Four Internal DMA Interrupts
— Cache-Off Mode
— Separate, Non-maskable Interrupt Pin
High Bandwidth On-Chip Data RAM
— Context Switch in 625 ns Typical
— 1 Kbyte On-Chip Data RAM
s
On-Chip Data Cache
— Sustains 128 bits per Clock Access
— 1 Kbyte Direct-Mapped, Write Through
Selectable Big or Little Endian Byte
— 128 bits per Clock Access on Cache Hit
Ordering
s
s
s
s
s
s
© INTEL CORPORATION, 1996
June 1996
Order Number:
272886-001
Information in this document is provided in connection with Intel products. No license, express or implied, by
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in
Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel
disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or
warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright
or other intellectual property right. Intel products are not intended for use in medical, life saving, or life
sustaining applications.
Intel retains the right to make changes to specifications and product descriptions at any time, without notice.
*Third-party brands and names are the property of their respective owners.
Copies of documents which have an ordering number and are referenced in this document, or other Intel
literature, may be obtained from:
Intel Corporation
P.O. Box 7641
Mt. Prospect IL 60056-764
or call 1-800-548-4725
A
80960CF-40, -33, -25, -16
32-BIT HIGH-PERFORMANCE SUPERSCALAR
EMBEDDED MICROPROCESSOR
CONTENTS
1.0 PURPOSE .................................................................................................................................................. 1
2.0 80960CF OVERVIEW ................................................................................................................................ 1
2.1 The 80960C-Series Core .................................................................................................................... 3
2.2 Pipelined, Burst Bus ........................................................................................................................... 3
2.3 Instruction Set Summary .................................................................................................................... 3
2.4 Flexible DMA Controller ...................................................................................................................... 3
2.5 Priority Interrupt Controller .................................................................................................................. 4
3.0 PACKAGE INFORMATION ........................................................................................................................ 5
3.1 Package Introduction .......................................................................................................................... 5
3.2 Pin Descriptions .................................................................................................................................. 5
3.3 80960CF Mechanical Data ............................................................................................................... 12
3.3.1 80960CF PGA PINOUT ......................................................................................................... 12
3.3.2 80960CF PQFP Pinout (80960CF-33, -25, -16 Only) ............................................................ 16
3.4 Package Thermal Specifications ...................................................................................................... 19
3.5 Stepping Register Information .......................................................................................................... 22
3.6 Sources for Accessories ................................................................................................................... 22
4.0 ELECTRICAL SPECIFICATIONS ............................................................................................................ 23
4.1 Absolute Maximum Ratings .............................................................................................................. 23
4.2 Operating Conditions ........................................................................................................................ 23
4.3 Recommended Connections ............................................................................................................ 24
4.4 DC Specifications ............................................................................................................................. 24
4.5 AC Specifications .............................................................................................................................. 26
4.5.1 AC TEST CONDITIONS ........................................................................................................ 36
4.5.2 AC TIMING WAVEFORMS .................................................................................................... 37
4.5.3 DERATING CURVES ............................................................................................................. 41
5.0 RESET, BACKOFF AND HOLD ACKNOWLEDGE ................................................................................ 42
6.0 BUS WAVEFORMS .................................................................................................................................. 44
7.0 REVISION HISTORY ............................................................................................................................... 71
PRELIMINARY
iii
CONTENTS
A
80960CF Block Diagram ............................................................................................................ 2
80960CF PGA Pinout—View from Top (Pins Facing Down) .................................................... 12
80960CF PGA Pinout — View from Bottom (Pins Facing Up) ................................................. 13
80960CF PQFP Pinout—Top View (80960CF-33, -25, -16 Only) ............................................ 19
Measuring 80960CF PGA and PQFP Case Temperature ....................................................... 20
Register g0 ............................................................................................................................... 22
AC Test Load ........................................................................................................................... 37
Input and Output Clocks Waveform ......................................................................................... 37
CLKIN Waveform ..................................................................................................................... 37
Output Delay and Float Waveform ........................................................................................... 38
Input Setup and Hold Waveform .............................................................................................. 38
NMI, XINT7:0 Input Setup and Hold Waveform ....................................................................... 39
Hold Acknowledge Timings ...................................................................................................... 39
Bus Backoff (BOFF) Timings ................................................................................................... 40
Relative Timings Waveforms ................................................................................................... 40
Output Delay or Hold vs. Load Capacitance ............................................................................ 41
Rise and Fall Time Derating at Highest Operating Temperature and Minimum V
CC
............... 41
I
CC
vs. Frequency and Temperature—80960CF-33, -25, -16 .................................................. 42
I
CC
vs. Frequency and Temperature—80960CF-40 ................................................................ 42
Cold Reset Waveform .............................................................................................................. 44
Warm Reset Waveform ............................................................................................................ 45
Entering the ONCE State ......................................................................................................... 46
Clock Synchronization in the 2-x Clock Mode .......................................................................... 47
Clock Synchronization in the 1-x Clock Mode .......................................................................... 47
Non-Burst, Non-Pipelined Requests Without Wait States ........................................................ 48
Non-Burst, Non-Pipelined Read Request With Wait States ..................................................... 49
Non-Burst, Non-Pipelined Write Request With Wait States ..................................................... 50
Burst, Non-Pipelined Read Request Without Wait States, 32-Bit Bus ..................................... 51
Burst, Non-Pipelined Read Request With Wait States, 32-Bit Bus .......................................... 52
Burst, Non-Pipelined Write Request Without Wait States, 32-Bit Bus ..................................... 53
Burst, Non-Pipelined Write Request With Wait States, 32-Bit Bus .......................................... 54
Burst, Non-Pipelined Read Request With Wait States, 16-Bit Bus .......................................... 55
Burst, Non-Pipelined Read Request With Wait States, 8-Bit Bus ............................................ 56
Non-Burst, Pipelined Read Request Without Wait States, 32-Bit Bus ..................................... 57
Non-Burst, Pipelined Read Request With Wait States, 32-Bit Bus .......................................... 58
Burst, Pipelined Read Request Without Wait States, 32-Bit Bus ............................................. 59
Burst, Pipelined Read Request With Wait States, 32-Bit Bus .................................................. 60
Burst, Pipelined Read Request With Wait States, 16-Bit Bus .................................................. 61
Burst, Pipelined Read Request With Wait States, 8-Bit Bus .................................................... 62
FIGURES
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
iv
PRELIMINARY
A
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Figure 49.
Figure 50.
TABLES
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
CONTENTS
Using External READY ............................................................................................................ 63
Terminating a Burst with BTERM ............................................................................................. 64
BOFF Functional Timing .......................................................................................................... 65
HOLD Functional Timing .......................................................................................................... 66
DREQ and DACK Functional Timing ....................................................................................... 67
EOP Functional Timing ............................................................................................................ 67
Terminal Count Functional Timing ........................................................................................... 68
FAIL Functional Timing ............................................................................................................ 68
A Summary of Aligned and Unaligned Transfers for Little Endian Regions ............................. 69
A Summary of Aligned and Unaligned Transfers for Little Endian Regions (Continued) ......... 70
Idle Bus Operation ................................................................................................................... 71
80960CF Instruction Set ............................................................................................................ 4
80960CF Pin Description — External Bus Signals .................................................................... 6
80960CF Pin Description — Processor Control Signals ............................................................ 9
80960CF Pin Description — DMA and Interrupt Unit Control Signals ..................................... 11
80960CF PGA Pinout — In Signal Order ................................................................................ 14
80960CF PGA Pinout — In Pin Order ..................................................................................... 15
80960CF PQFP Pinout — In Signal Order (80960CF-33, -25, -16 Only) ................................ 17
80960CF PQFP Pinout — In Pin Order (80960CF-33, -25, -16 Only) ..................................... 18
Maximum T
A
at Various Airflows in
o
C (PGA Package Only) ................................................... 20
80960CF PGA Package Thermal Characteristics ................................................................... 21
80960CF PQFP Package Thermal Characteristics ................................................................. 21
Die Stepping Cross Reference ................................................................................................ 22
Operating Conditions ............................................................................................................... 23
DC Characteristics ................................................................................................................... 24
80960CF AC Characteristics (40 MHz) ................................................................................... 26
80960CF AC Characteristics (33 MHz) ................................................................................... 29
80960CF AC Characteristics (25 MHz) ................................................................................... 32
80960CF AC Characteristics (16 MHz) ................................................................................... 34
Reset Conditions ..................................................................................................................... 43
Hold Acknowledge and Backoff Conditions ............................................................................. 43
PRELIMINARY
v
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