80960JD-33 datasheet, PDF - EEWORLD Datasheet

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80960JD-33: DescriptionEMBEDDED 32-BIT MICROPROCESSOR; File Size337KB，61 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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80960JD-33 Overview

EMBEDDED 32-BIT MICROPROCESSOR

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PRELIMINARY

80960JD

EMBEDDED 32-BIT MICROPROCESSOR

Pin/Code Compatible with all 80960Jx

Processors

High-Performance Embedded Architecture

— One Instruction/Clock Execution

— Core Clock Rate is 2x the Bus Clock

— Load/Store Programming Model

— Sixteen 32-Bit Global Registers

— Sixteen 32-Bit Local Registers (8 sets)

— Nine Addressing Modes

— User/Supervisor Protection Model

Two-Way Set Associative Instruction Cache

— 80960JD - 4 Kbyte

— Programmable Cache Locking

Mechanism

Direct Mapped Data Cache

— 80960JD - 2 Kbyte

— Write Through Operation

On-Chip Stack Frame Cache

— Seven Register Sets Can Be Saved

— Automatic Allocation on Call/Return

— 0-7 Frames Reserved for High-Priority

Interrupts

On-Chip Data RAM

— 1 Kbyte Critical Variable Storage

— Single-Cycle Access

High Bandwidth Burst Bus

— 32-Bit Multiplexed Address/Data

— Programmable Memory Configuration

— Selectable 8-, 16-, 32-Bit Bus Widths

— Supports Unaligned Accesses

— Big or Little Endian Byte Ordering

New Instructions

— Conditional Add, Subtract and Select

— Processor Management

High-Speed Interrupt Controller

— 31 Programmable Priorities

— Eight Maskable Pins plus NMI

— Up to 240 Vectors in Expanded Mode

Two On-Chip Timers

— Independent 32-Bit Counting

— Clock Prescaling by 1, 2, 4 or 8

— lnternal Interrupt Sources

Halt Mode for Low Power

Compatibility

IEEE 1149.1 (JTAG) Boundary Scan

Packages

— 132-Lead Pin Grid Array (PGA)

— 132-Lead Plastic Quad Flat Pack (PQFP)

132

PIN 1

A80960JD

XXXXXXXXA2

i960

NG80960JD

XXXXXXXXA2

Figure 1. 80960JD Microprocessor

Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any

patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Information

contained herein supersedes previously published specifications on these devices from Intel.

September 1995

Order Number: 272596-002

80960JD

EMBEDDED 32-BIT MICROPROCESSOR

1.0 PURPOSE ..................................................................................................................................................1

2.0 80960JD OVERVIEW ................................................................................................................................. 1

2.1 80960 Processor Core ........................................................................................................................2

2.2 Burst Bus ............................................................................................................................................2

2.3 Timer Unit ...........................................................................................................................................3

2.4 Priority Interrupt Controller .................................................................................................................3

2.5 Instruction Set Summary ....................................................................................................................3

2.6 Faults and Debugging .........................................................................................................................3

2.7 Low Power Operation .........................................................................................................................4

2.8 Test Features ......................................................................................................................................4

2.9 Memory-Mapped Control Registers ....................................................................................................4

2.10 Data Types and Memory Addressing Modes ....................................................................................4

3.0 PACKAGE INFORMATION ........................................................................................................................6

3.1 Pin Descriptions .................................................................................................................................. 6

3.1.1 Functional Pin Definitions ........................................................................................................6

3.1.2 80960Jx 132-Lead PGA Pinout .............................................................................................13

3.1.3 80960Jx PQFP Pinout ...........................................................................................................17

3.2 Package Thermal Specifications ......................................................................................................20

3.3 Thermal Management Accessories ..................................................................................................22

4.0 ELECTRICAL SPECIFICATIONS ............................................................................................................23

4.1 Absolute Maximum Ratings ..............................................................................................................23

4.2 Operating Conditions ........................................................................................................................23

4.3 Connection Recommendations .........................................................................................................24

4.4 DC Specifications .............................................................................................................................24

4.5 AC Specifications ..............................................................................................................................26

4.5.1 AC Test Conditions and Derating Curves ...............................................................................33

4.5.2 AC Timing Waveforms ............................................................................................................34

5.0 BUS FUNCTIONAL WAVEFORMS .........................................................................................................42

6.0 DEVICE IDENTIFICATION .......................................................................................................................56

7.0 REVISION HISTORY ...............................................................................................................................56

PRELIMINARY

80960JD

FIGURES

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Figure 10.

Figure 11.

Figure 12.

Figure 13.

Figure 14.

Figure 15.

Figure 16.

Figure 17.

Figure 18.

Figure 19.

Figure 20.

Figure 21.

Figure 22.

Figure 23.

Figure 24.

Figure 25.

Figure 26.

Figure 27.

Figure 28.

Figure 29.

Figure 30.

Figure 31.

Figure 32.

Figure 33.

Figure 34.

Figure 35.

Figure 36.

80960JD Microprocessor ...........................................................................................................0

80960JD Block Diagram ............................................................................................................2

132-Lead Pin Grid Array Bottom View - Pins Facing Up .......................................................... 13

132-Lead Pin Grid Array Top View - Pins Facing Down ........................................................... 14

132-Lead PQFP - Top View ..................................................................................................... 17

50 MHz Maximum Allowable Ambient Temperature ................................................................ 21

40 MHz Maximum Allowable Ambient Temperature ................................................................ 22

AC Test Load ............................................................................................................................ 33

Output Delay or Hold vs. Load Capacitance ............................................................................ 33

Rise and Fall Time Derating ..................................................................................................... 34

CLKIN Waveform ..................................................................................................................... 34

Output Delay Waveform for T

OV1

............................................................................................. 35

Output Float Waveform for T

................................................................................................ 35

Input Setup and Hold Waveform for T

IS1

and T

IH1

................................................................... 36

Input Setup and Hold Waveform for T

IS2

and T

IH2

................................................................... 36

Input Setup and Hold Waveform for T

IS3

and T

IH3

................................................................... 37

Input Setup and Hold Waveform for T

IS4

and T

IH4

................................................................... 37

Relative Timings Waveform for T

LXL

and T

LXA

......................................................................... 38

DT/R and DEN Timings Waveform .......................................................................................... 38

TCK Waveform ......................................................................................................................... 39

Input Setup and Hold Waveforms for T

BSIS1

and T

BSIH1

......................................................... 39

Output Delay and Output Float Waveform for T

BSOV1

and T

BSOF1

.......................................... 40

Output Delay and Output Float Waveform for T

BSOV2

and T

BSOF2

.......................................... 40

Input Setup and Hold Waveform for T

BSIS2

and T

BSIH2

........................................................... 41

Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus ............................... 42

Burst Read and Write Transactions Without Wait States, 32-Bit Bus ...................................... 43

Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus ................................................ 44

Burst Read and Write Transactions Without Wait States, 8-Bit Bus ........................................ 45

Burst Read and Write Transactions With 1, 0 Wait States

and Extra Tr State on Read, 16-Bit Bus ................................................................................... 46

Bus Transactions Generated by Double Word Read Bus Request,

Misaligned One Byte From Quad Word Boundary, 32-Bit Bus, Little Endian ........................... 47

HOLD/HOLDA Waveform For Bus Arbitration .......................................................................... 48

Cold Reset Waveform .............................................................................................................. 49

Warm Reset Waveform ............................................................................................................ 50

Entering the ONCE State ......................................................................................................... 51

Summary of Aligned and Unaligned Accesses (32-Bit Bus) .................................................... 54

Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued) ................................ 55

iii

PRELIMINARY

80960JD

TABLES

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

80960Jx Instruction Set ................................................................................................................ 5

Pin Description Nomenclature ...................................................................................................... 6

Pin Description — External Bus Signals ...................................................................................... 7

Pin Description — Processor Control Signals, Test Signals and Power ..................................... 10

Pin Description — Interrupt Unit Signals .................................................................................... 12

132-Lead PGA Pinout — In Signal Order ................................................................................... 15

132-Lead PGA Pinout — In Pin Order ....................................................................................... 16

132-Lead PQFP Pinout — In Signal Order ................................................................................ 18

132-Lead PQFP Pinout — In Pin Order ..................................................................................... 19

132-Lead PGA Package Thermal Characteristics ...................................................................... 20

132-Lead PQFP Package Thermal Characteristics ................................................................... 21

80960JD Operating Conditions .................................................................................................. 23

80960JD DC Characteristics ...................................................................................................... 24

80960JD I

Characteristics ...................................................................................................... 25

80960JD AC Characteristics (50 MHz) ...................................................................................... 26

Note Definitions for Table 15, 80960JD AC Characteristics (50 MHz) ...................................... 28

80960JD AC Characteristics (40 MHz) ...................................................................................... 28

80960JD AC Characteristics (33 MHz) ...................................................................................... 31

Natural Boundaries for Load and Store Accesses ..................................................................... 52

Summary of Byte Load and Store Accesses .............................................................................. 52

Summary of Short Word Load and Store Accesses ................................................................... 52

Summary of n-Word Load and Store Accesses (n = 1, 2, 3, 4) .................................................. 53

80960JD Die and Stepping Reference ....................................................................................... 56

Data Sheet Version -001 to -002 Revision History ..................................................................... 56

PRELIMINARY

80960JD-33 Related Products

	80960JD-33	80960JD-40	80960JD-50
Description	EMBEDDED 32-BIT MICROPROCESSOR	EMBEDDED 32-BIT MICROPROCESSOR	EMBEDDED 32-BIT MICROPROCESSOR

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