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COPYRIGHT
INTEL CORPORATION 1995
January 1995
Order Number 271328-001
SPECIAL ENVIRONMENT 80960CF-30 -25 -16
271328 – 1
Figure 1 80960CF Die Photo
2
Special Environment 80960CF-30 -25 -16
32-Bit High Performance Superscalar Processor
CONTENTS
1 0 PURPOSE
2 0 i960 CF PROCESSOR
OVERVIEW
2 1 The C-Series Core
2 2 Pipelined Burst Bus
2 3 Flexible DMA Controller
2 4 Priority Interrupt Controller
2 5 Instruction Set Summary
3 0 PACKAGE INFORMATION
3 1 Package Introduction
3 2 Pin Descriptions
3 3 80960CF Pinout
3 4 Mechanical Data
3 5 Package Thermal Specifications
3 6 Stepping Register Information
3 7 Suggested Sources for 80960CF
Accessories
4 0 ELECTRICAL SPECIFICATIONS
4 1 Absolute Maximum Ratings
4 2 Operating Conditions
4 3 Recommended Connections
4 4 DC Specifications
4 5 AC Specifications
5 0 RESET BACKOFF AND HOLD
ACKNOWLEDGE
6 0 BUS WAVEFORMS
PAGE
5
5
6
6
6
6
7
8
8
8
14
18
20
21
21
22
22
22
22
23
24
35
36
CONTENTS
FIGURES
Figure 1
Figure 2
Figure 3
Figure 4a
Figure 4b
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10a
Figure 10b
Figure 11
Figure 12a
Figure 12b
Figure 13
Figure 14
80960CF Die Photo
80960CF Block Diagram
Example Pin Description
Entry
80960CF PGA Pinout (View
from Top Side)
80960CF PGA Pinout (View
from Bottom Side)
168-Lead Ceramic PGA
Package Dimensions
80960CF PGA Package
Thermal Characteristics
Measuring 80960CF PGA
Case Temperature
Register G0
AC Test Load
Input and Output Clocks
Waveform
CLKIN Waveform
Output Delay and Float
Waveform
Input Setup and Hold
Waveform
NMI XINT7 0 Input Setup
and Hold Waveform
Hold Acknowledge
Timings
Bus Back-Off (BOFF)
Timings
PAGE
2
5
8
16
17
18
20
21
21
30
30
30
31
31
31
32
32
3
CONTENTS
Figure 15
PAGE
33
33
CONTENTS
Figure 31
PAGE
Relative Timings
Waveforms
Figure 16 Output Delay or Hold vs Load
Capacitance
Figure 17 Rise and Fall Time Derating at
Highest Operating
Temperature and Minimum
V
CC
Figure 18 I
CC
vs Frequency and
Temperature
Figure 19 Cold Reset Waveform
Figure 20 Warm Reset Waveform
Figure 21 Entering the ONCE State
Figure 22a Clock Synchronization in the
2x Clock Mode
Figure 22b Clock Synchronization in the
1x Clock Mode
Figure 23 Non-Burst Non-Pipelined
Requests without Wait
States
Figure 24 Non-Burst Non-Pipelined
Read Request with Wait
States
Figure 25 Non-Burst Non-Pipelined
Write Request with Wait
States
Figure 26 Burst Non-Pipelined Read
Request without Wait States
32-Bit Bus
Figure 27 Burst Non-Pipelined Read
Request with Wait States
32-Bit Bus
Figure 28 Burst Non-Pipelined Write
Request without Wait States
32-Bit Bus
Figure 29 Burst Non-Pipelined Write
Request with Wait States
32-Bit Bus
Figure 30 Burst Non-Pipelined Read
Request with Wait States
16-Bit Bus
Figure 32
Figure 33
34
34
36
37
38
39
39
Figure 34
Figure 35
Figure 36
Figure 37
40
Figure 38
Figure 39
41
42
Figure 40
Figure 41
Figure 42
Figure 43
Figure 44
Figure 45
Figure 46
43
44
45
Figure 47
46
47
Figure 48
Burst Non-Pipelined Read
Request with Wait States
8-Bit Bus
Non-Burst Pipelined Read
Request without Wait States
32-Bit Bus
Non-Burst Pipelined Read
Request with Wait States
32-Bit Bus
Burst Pipelined Read
Request without Wait States
32-Bit Bus
Burst Pipelined Read
Requests with Wait States
32-Bit Bus
Burst Pipelined Read
Requests with Wait States
16-Bit Bus
Burst Pipelined Read
Requests with Wait States
8-Bit Bus
Using External READY
Terminating a Burst with
BTERM
BOFF Functional Timing
HOLD Functional Timing
DREQ and DACK Functional
Timing
EOP Functional Timing
Terminal Count Functional
Timing
FAIL Functional Timing
A Summary of Aligned and
Unaligned Transfers for Little
Endian Regions
A Summary of Aligned and
Unaligned Transfers for Little
Endian Regions
(Continued)
Idle Bus Operation
48
49
50
51
52
53
54
55
56
57
57
58
58
59
59
60
61
62
4
SPECIAL ENVIRONMENT 80960CF-30 -25 -16
tions every clock and peak at execution of three
instructions per clock
A 32-bit demultiplexed and pipelined burst bus pro-
vides a 132 Mbyte s bandwidth to a system’s high-
speed external memory sub-system In addition the
80960CF’s on-chip caching of instructions proce-
dure context and critical program data substantially
decouples system performance from the wait states
associated with accesses to the system’s slower
cost sensitive main memory sub-system
The 80960CF bus controller also integrates full wait
state and bus width control for highest system per-
formance with minimal system design complexity
Unaligned access and Big Endian byte order support
reduces the cost of porting existing applications to
the 80960CF
The processor also integrates four complete data-
chaining DMA channels and a high-speed interrupt
controller on-chip The DMA channels perform sin-
gle-cycle or two-cycle transfers data packing and
unpacking and data chaining Block transfers in ad-
dition to source or destination synchronized trans-
fers are provided
The interrupt controller provides full programmability
of 248 interrupt sources into 32 priority levels with a
typical interrupt task switch (‘‘latency’’) time of
750 ns
10
PURPOSE
This document previews electrical characterizations
of Intel’s i960 CF embedded microprocessor (avail-
able in 33 25 and 16 MHz) For a detailed descrip-
tion of any i960 CF processor functional topic oth-
er than parametric performance refer to the latest
i960 CA Microprocessor Reference Manual (Order
No 270710) and the
i960 CF Reference Manual Ad-
dendum
(Order No 272188)
20
i960 CF PROCESSOR OVERVIEW
Intel’s i960 CF microprocessor is the performance
follow-on product to the i960 CA processor The
i960 CF product is socket- and object code-compati-
ble with the CA this makes CA-to-CF design up-
grades straightforward The i960 CF processor’s in-
struction cache is 4 Kbytes (CA device has 1 Kbyte)
CF data cache is 1 Kbyte (CA device has no data
cache) This extra cache on the CF product adds a
significant performance boost over the CA The
80960CF is object code compatible with the 32-bit
80960 Core Architecture while including Special
Function Register extensions to control on-chip pe-
ripherals and instruction set extensions to shift 64-
bit operands and configure on-chip hardware Multi-
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