EPM570F100A4N datasheet, PDF - EEWORLD Datasheet

EPM570F100A4N: DescriptionFlash PLD, 7ns, 440-Cell, CMOS, PBGA100, 11 X 11 MM, 1 MM PITCH, LEAD FREE, FBGA-100; CategoryProgrammable logic devices Programmable logic; File Size1MB，86 Pages; ManufacturerIntel; Websitehttp://www.intel.com/; Environmental Compliance

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EPM570F100A4N Overview

Flash PLD, 7ns, 440-Cell, CMOS, PBGA100, 11 X 11 MM, 1 MM PITCH, LEAD FREE, FBGA-100

Parameter Name	Attribute value
Is it Rohs certified?	conform to
package instruction	LBGA, BGA100,10X10,40
Reach Compliance Code	compliant
Other features	IT CAN ALSO OPERATE AT 3.3V
In-system programmable	YES
JESD-30 code	S-PBGA-B100
JESD-609 code	e1
JTAG BST	YES
length	11 mm
Dedicated input times
Number of I/O lines	76
Number of macro cells	440
Number of terminals	100
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
organize	0 DEDICATED INPUTS, 76 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA100,10X10,40
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE
Peak Reflow Temperature (Celsius)	260
power supply	1.5/3.3,2.5/3.3 V
Programmable logic type	FLASH PLD
propagation delay	7 ns
Certification status	Not Qualified
Maximum seat height	1.7 mm
Maximum supply voltage	2.625 V
Minimum supply voltage	2.375 V
Nominal supply voltage	2.5 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
width	11 mm
Base Number Matches	1

Section I. MAX II Device Family Data

Sheet

This section provides designers with the data sheet specifications for MAX

II devices.

The chapters contain feature definitions of the internal architecture, Joint Test Action

Group (JTAG) and in-system programmability (ISP) information, DC operating

conditions, AC timing parameters, and ordering information for MAX II devices.

This section includes the following chapters:

■

Chapter 1, Introduction

Chapter 2, MAX II Architecture

Chapter 3, JTAG and In-System Programmability

Chapter 4, Hot Socketing and Power-On Reset in MAX II Devices

Chapter 5, DC and Switching Characteristics

Chapter 6, Reference and Ordering Information

Revision History

Refer to each chapter for its own specific revision history. For information about when

each chapter was updated, refer to the Chapter Revision Dates section, which appears

in the complete handbook.

Altera Corporation

MAX II Device Handbook

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