EPM1270F100C5ES datasheet, PDF

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EPM1270F100C5ES: DescriptionFlash PLD, PBGA100, 11 X 11 MM, 1 MM PITCH, FBGA-100; CategoryProgrammable logic devices Programmable logic; File Size1MB，98 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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EPM1270F100C5ES Overview

Flash PLD, PBGA100, 11 X 11 MM, 1 MM PITCH, FBGA-100

EPM1270F100C5ES Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
package instruction	BGA,
Reach Compliance Code	compliant
Other features	IT CAN ALSO OPERATE AT 3.3V
JESD-30 code	S-PBGA-B100
JESD-609 code	e0
Dedicated input times
Number of I/O lines
Number of terminals	100
organize	0 DEDICATED INPUTS, 0 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Programmable logic type	FLASH PLD
Certification status	Not Qualified
Maximum supply voltage	2.625 V
Minimum supply voltage	2.375 V
Nominal supply voltage	2.5 V
surface mount	YES
Terminal surface	TIN LEAD
Terminal form	BALL
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
Base Number Matches	1

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Section I. MAX II Device

Family Data Sheet

This section provides designers with the data sheet specifications for

MAX

II devices. The chapters contain feature definitions of the internal

architecture, Joint Test Action Group (JTAG) and in-system

programmability (ISP) information, DC operating conditions, AC timing

parameters, and ordering information for MAX II devices.

This section includes the following chapters:

■

Chapter 1. Introduction

Chapter 2. MAX II Architecture

Chapter 3. JTAG & In-System Programmability

Chapter 4. Hot Socketing & Power-On Reset in MAX II Devices

Chapter 5. DC & Switching Characteristics

Chapter 6. Reference & Ordering Information

Revision History

The table below shows the revision history for

Chapters 1

through

Chapter(s)

Date/Version

August 2006, v1.5

July 2006, v1.4

June 2005, v1.3

Changes Made

Minor update to features list.

Minor updates to tables.

Updated timing numbers in Table 1-1.

December 2004, v1.2 Updated timing numbers in Table 1-1.

June 2004, v1.1

August 2006, v1.6

Updated timing numbers in Table 1-1.

Updated functional description and I/O

structure sections.

Altera Corporation

Section I–1

Preliminary

Chapter 1. Introduction

MII51001-1.5

Introduction

The MAX

II family of instant-on, non-volatile CPLDs is based on a

0.18-µm, 6-layer-metal-flash process, with densities from 240 to 2,210

logic elements (LEs) (128 to 2,210 equivalent macrocells) and non-volatile

storage of 8 Kbits. MAX II devices offer high I/O counts, fast

performance, and reliable fitting versus other CPLD architectures.

Featuring MultiVolt™ core, a user flash memory (UFM) block, and

enhanced in-system programmability (ISP), MAX II devices are designed

to reduce cost and power while providing programmable solutions for

applications such as bus bridging, I/O expansion, power-on reset (POR)

and sequencing control, and device configuration control.

The following shows the main sections of the MAX II CPLD Family Data

Sheet:

Section

Page

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Logic Array Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

Logic Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8

MultiTrack Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15

Global Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

User Flash Memory Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23

MultiVolt Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27

I/O Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–28

IEEE Std. 1149.1 (JTAG) Boundary Scan Support . . . . . . . . . . 3–1

In System Programmability . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4

Hot Socketing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

Power-On Reset Circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9

Timing Model & Specifications . . . . . . . . . . . . . . . . . . . . . . . . 5–10

Device Pin-Outs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1

Altera Corporation

August 2006

Core Version a.b.c variable

1–1

Preliminary

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