Standard Products
UT4090 RadHard FPGA
Advanced Data Sheet
August 3, 2001, Rev D
EV
q
One-time programmable, ViaLink
T M
antifuse technology
for personalization
q
150 MHz 16-bit counters, 200 MHz datapaths, 80+ MHz
FIFOs
q
90,000 usable PLD gates (non-volatile)
q
I/Os
- Interfaces with both 3.3 volt and 5 volt devices
- PCI compliant with 3.3V and 5V busses
- Full JTAG 1149.1 compliant
- Registered I/O cells with individually controlled clocks
and output enables
q
Radiation-hardened design; total dose irradiation testing to
MIL-STD-883 Test Method 1019
- Total-dose: 30 krad(Si)
- SEL Immune TBD
- LET
TH
(0.25) TBD
- Saturated Cross Section cm per bit - TBD
q
22 dual-port RAM modules, organized in user-configurable
1,152 bit blocks
- 5ns access times, each port independently accessible
- Fast and efficient for FIFO, RAM, and ROM functions
q
100% routable with 100% utilization and complete pin-out
stability
q
Variable-grain logic cells provide high performance and
100% utilization
2
D
IN
EL
O
The UT4090 RadHard Field Programmable Gate Array (FPGA)
offers 90,000 usable PLD gates including Dual-Port SRAM
modules. It is fabricated on 0.35µm four-layer metal CMOS
process. The UT4090 contains 1,584 logic cells and 22 dual port
RAM modules (see Figure 1). Each RAM module has 1,152
RAM bits, for a total of 25,344 bits. RAM modules are Dual
Port (one read port, one write port) and can be configured into
one of four modes: 64 (deep) x 18(wide), 128x9, 256x4, or
512x2 (see Figure 2). The UT4090 is available in a 208-pin
Cerquad Flatpack, allowing access to 166 bidirectional signal I/
O, 8 high drive inputs, and 5 JTAG I/O.
Designers can cascade multiple RAM modules to increase the
depth or width allowed in single modules by connecting
corresponding address lines together and dividing the words
between modules (see Figure 3). This approach allows a variety
of address depths and word widths to be tailored to a specific
application.
Aeroflex UTMC uses QuickLogic Corporation’s licensed ESP
(Embedded Standard Products) technology for the UT4090.
QuickLogic is a pioneer in the FPGA semiconductor and the
software tools field.
PM
EN
T
Interface
FEATURES
q
0.35µm four-layer metal, anti-fuse epitaxial CMOS process
for smallest die sizes
q
Comprehensive design tools include high quality Verilog/
VHDL synthesis and simulation
q
QuickLogic existing IP such as microcontrollers, DRAM
controllers, USART and PCI can be accessed
q
Packaged in a 208-pin Cerquad Flatpack
q
Standard Microcircuit Drawing TBD
- QML Q and T compliant part
INTRODUCTION
IP
22
RAM
Blocks
1,584
High Speed
Logic Cells
Figure 1. UT4090 FPGA Block Diagram
1
Q
WA(8:0)
WD(17:0)
WE
WCLK
MODE(1:0)
RE
D
RCLK
RA(8:0)
RD(17:0)
ASYNCRD
GE
GCLK
GR
I
E
OA
OB
E
R
Q
EN
Figure 4. UT4090 FPGA I/O Cell
T
PAD
Figure 2. UT4090 FPGA RAM Module
EV
RDATA
RADDR
RDATA
3
Software support for the UT4090 is available from QuickLogic.
The turnkey QuickWorks
TM
package provides the most com-
plete software solution from design entry to logic synthesis,
place and route, simulation and static timing analysis. The
QuickTools
TM
for Workstations package provides a solution
for designers who use Cadence, Exemplar, Mentor, Synopsys,
Synplicity, Viewlogic, Veribest or other third-party tools for
design entry, synthesis or simulation. Please visit Quick Logic’s
website at www.quicklogic.com for more information.
IN
The UT4090 variable grain logic cell features up to 16 simulta-
neous inputs and 5 outputs within a cell that can be fragmented
into 5 independent cells. Each cell has a fan-in of 29 including
register and control lines (see Figure 5).
D
WDATA
RAM
Module
(1,152 bits)
WADDR
RAM
Module
(1,152 bits)
WDATA
Figure 3. UT4090 FPGA Module Bits
EL
O
I/O Pins
PRODUCT DESCRIPTION
• 308 bi-directional input/output pins, PCI-compliant for 5V
and 3.3V buses (see Figure 4)
• 8 high-drive input distributed network pins
Distributed Networks
• Two array clock/control networks available to the logic cell
flip-flop clock, set and reset inputs - each driven by an input-
only pin
• Six global clock/control networks available to the logic cell
F1, flip-flop clock, set and reset inputs and the input and I/O
register clock, reset and enable inputs, as well as the output
enable control - each driven by an input-only or I/O pin, or
any logic cell output, or I/O cell feedback.
Performance
• Input + logic cell + output total delays under 12ns
• Data path speeds over 200 MHz
• Counter speeds over 150 MHz
• FIFO speeds over 80+ MHz
PM
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