FEMTOCLOCKS™ CRYSTAL-TO-LVPECL
350MHZ FREQUENCY MARGINING SYNTHESIZER
ICS843207-350
G
ENERAL
D
ESCRIPTION
T h e I C S 8 4 3 2 0 7 - 3 5 0 i s a l ow p h a s e - n o i s e
IC
S
frequency margining synthesizer that targets
HiPerClockS™
clocking for high performance interfaces such
as SPI4.2 and is a member of the HiPerClockS™
family of high performance clock solutions from
IDT. In the default mode, each output can be configured
individually to generate an 87.5MHz, 175MHZ or 350MHz
LVPECL output clock signal from a 14MHz crystal input.
There is also a frequency margining mode available where
the device can be configured, using control pins, to vary
the output frequency up or down from nominal by 5%. The
ICS843207-350 is provided in a 48-pin LQFP package.
F
EATURES
•
Seven independently configurable LVPECL outputs at
87.5MHz, 175MHz or 350MHz
•
Individual high impedance control of each output
•
Selectable crystal oscillator interface designed for 14MHz,
18pF parallel resonant crystal or LVCMOS single-ended input
• Output frequency can be varied ± 5% from nominal
• VCO range: 620MHz - 750MHz
• Full 3.3V supply mode
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
P
IN
A
SSIGNMENT
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
33
4
5
32
48-Pin LQFP
6
7mm x 7mm x 1.4mm
31
package body
30
7
Y Package
8
29
Top View
9
28
27
10
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
SEL2
SEL3
SEL4
SEL5
SEL6
SEL7
SEL8
SEL9
SEL10
SEL11
SEL12
SEL13
V
CCO
Q0
nQ0
Q1
nQ1
V
EE
V
CCO
Q2
nQ2
Q3
nQ3
V
CCO
ICS843207-350
V
CCA
V
CC
V
CCO
nQ6
Q6
V
EE
V
CCO
nQ5
Q5
nQ4
Q4
V
CCO
B
LOCK
D
IAGRAM
00 HiZ
01 ÷2
10 ÷8
11 ÷4
Q0
nQ0
Pullup
2
SEL[1:0]
00 HiZ
01 ÷2
10 ÷8
11 ÷4
Pullup
Q1
nQ1
2
SEL[3:2]
Q2
nQ2
IDT
™
/ ICS
™
LVPECL FREQUENCY MARGINING SYNTHESIZER
REF_CLK
V
EE
MR
MARGIN
MODE
SEL1
SEL0
nPLL_SEL
V
CC
XTAL_IN
XTAL_OUT
nXTAL_SEL
00 HiZ
01 ÷2
10 ÷8
11 ÷4
Pullup
nPLL_SEL
Pulldown
14MHz
2
SEL[5:4]
Q3
nQ3
XTAL_IN
OSC
1
0
0
00 HiZ
01 ÷2
10 ÷8
11 ÷4
Pullup
XTAL_OUT
REF_CLK
Pulldown
nXTAL_SEL
Pulldown
0
1
2
Predivider
÷2
1
Phase
Detector
SEL[7:6]
Q4
nQ4
VCO
620 - 750MHz
0
00 HiZ
01 ÷2
10 ÷8
11 ÷4
÷50
00 HiZ
01 ÷2
10 ÷8
11 ÷4
Pullup
2
SEL[9:8]
Q5
nQ5
1
÷95
÷105
MODE
Pulldown
MARGIN
Pulldown
MR
Pulldown
Pullup
2
SEL[11:10]
Q6
nQ6
To O/P Dividers
00 HiZ
01 ÷2
10 ÷8
11 ÷4
Pullup
2
SEL[13:12]
1
ICS843207CY-350 REV. A JANUARY 16, 2008
ICS843207-350
FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER
F
UNCTIONAL
D
ESCRIPTION
The ICS843207-350 features a fully integrated PLL and
therefore requires no external components for setting the loop
bandwidth. A 14MHz fundamental crystal is used as the input
to the on chip oscillator. The output of the oscillator is fed into
the pre-divider. In frequency margining mode, the 14MHz
crystal frequency is divided by 2 and a 7MHz reference
frequency is applied to the phase detector. The VCO of the
PLL operates over a range of 620MHz to 750MHz. The output
of the M divider is also applied to the phase detector. The
default mode for the ICS843207-350 is a nominal VCO
frequency of 700MHz with each output configurable to divide
by 2, 4 or 8. The nominal output frequency can be changed by
placing the device into the margining mode using the mode pin
and using the margin pin to change the M feedback divider.
Frequency margining mode operation occurs when the MODE
input is HIGH. The phase detector and the M divider force the
VCO output frequency to be M times the reference frequency
by adjusting the VCO control voltage. The output of the VCO is
scaled by an output divider prior to being sent to the LVPECL
output buffer. The divider provides a 50% output duty cycle.
The relationship between the crystal input frequency, the M
divider, the VCO frequency and the output frequency is provided
in Table 1A. When changing back from frequency margining
mode to nominal mode, the device will return to the default
nominal configuration described above.
T
ABLE
1A. F
REQUENCY
S
ELECT
F
UNCTION
T
ABLE
XTAL (MHz)
14
14
14
14
SELx
0
0
1
1
SELx-1
0
1
0
1
VCO (MHz)
700
700
700
700
Output Divider
N/ A
2
8
4
Output Frequency (MHz)
HiZ
350
87.5
175
T
ABLE
1B. F
REQUENCY
M
ARGIN
F
UNCTION
T
ABLE
MODE
1
0
1
MARGIN
0
X
1
XTAL (MHz)
14
14
14
Pre-Divider (P)
2
1
2
Feedback Divider
95
50
10 5
VCO (MHz)
665
700
735
% Change
-5.0
Nom. Mode
+5.0
IDT
™
/ ICS
™
LVPECL FREQUENCY MARGINING SYNTHESIZER
2
ICS843207CY-350 REV. A JANUARY 16, 2008
ICS843207-350
FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER
T
ABLE
2. P
IN
D
ESCRIPTIONS
Number
Number
1, 7, 12,
25, 30, 34
2, 3
4, 5
6, 16, 31
8, 9
10, 11
13
14
Name
Name
V
CCO
Q0, nQ0
Q1, nQ1
V
EE
Q2, nQ2
Q3, nQ3
MODE
Margin
Type
Type
Power
Ouput
Ouput
Power
Ouput
Ouput
Input
Input
Pulldown
Pulldown
Description
Description
Output supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Negative supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
MODE pin. LOW = default mode. HIGH = frequency margining mode.
See Table 4B. LVCMOS/LVTTL interface levels.
Sets the frequency to ±5% in frequency margining mode.
See Table 1B. LVCMOS/LVTTL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go LOW and inver ted outputs
nQx to go HIGH. When logic LOW, the internal dividers and the
outputs are enabled. LVCMOS/LVTTL interface levels.
Reference input clock. LVCMOS/LVTTL interface levels.
Cr ystal select pin. Selects between the cr ystal and the reference
clock inputs. LVCMOS/LVTTL interface levels.
Parallel resonant cr ystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Core supply pins.
PLL select pin. When HIGH, PLL is bypassed and input is fed directly
to the output dividers. When LOW, PLL is enabled.
LVCMOS/LVTTL interface levels.
15
17
18
19,
20
21, 35
22
23, 24,
37, 38,
39, 40,
41, 42,
43, 44,
45, 46,
47, 48
26, 27
28, 29
32, 33
36
MR
REF_CLK
nXTAL_SEL
XTAL_OUT,
XTAL_IN
V
CC
nPLL_SEL
SEL0, SEL1,
SEL2, SEL3,
SEL4, SEL5,
SEL6, SEL7,
SEL8, SEL9,
SEL10, SEL11,
SEL12, SEL13
Q4, nQ4
Q5, nQ5
Q6, nQ6
V
CCA
Input
Input
Input
Input
Power
Input
Pulldown
Pulldown
Pulldown
Pulldown
Input
Pullup
Output divider select pins. See Table 1A.
LVCMOS/LVTTL interface levels.
Ouput
Ouput
Ouput
Power
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Analog supply pin.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
3. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
T
ABLE
4A. nXTAL_SEL C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Input
nXTAL_SEL
0
1
Selected Source
XTAL_IN, XTAL_OUT
REF_CLK
T
ABLE
4B. M
ODE
C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Input
MODE
0
1
Condition
Q0:Q6, nQ0:nQ6
Default Mode
Frequency Margining Mode
IDT
™
/ ICS
™
LVPECL FREQUENCY MARGINING SYNTHESIZER
3
ICS843207CY-350 REV. A JANUARY 16, 2008
ICS843207-350
FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Package Thermal Impedance,
θ
JA
65.7°C/W (0 mps)
T
ABLE
5A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3.3V±5%, V
CCO
= V
EE
=
O
V, T
A
= 0°C
TO
70°C
Symbol Parameter
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
V
CC
– 0.13
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
V
CC
3.465
210
13
Units
V
V
V
mA
mA
T
ABLE
5B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3.3V±5%, V
EE
=
O
V, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
Input
High Current
REF_CLK, MARGIN,
MODE, nPLL_SEL,
MR, nXTAL_SEL
SEL[0:13]
REF_CLK, MARGIN,
MODE, nPLL_SEL,
MR, nXTAL_SEL
SEL[0:13]
Δ
t/
Δv
Input Transition
Rise/Fall Rate
SEL[0:13], MODE
Test Conditions
V
CC
= 3.3V
V
CC
= 3.3V
V
CC
= V
IN
= 3.465
V
CC
= V
IN
= 3.465
V
CC
= 3.465V,
V
IN
= 0V
V
CC
= 3.465V,
V
IN
= 0V
-5
-150
20
Minimum Typical
2
-0.3
Maximum
V
CC
+ 0.3
0.8
15 0
5
Units
V
V
µA
µA
µA
µA
ns/V
I
IL
Input
Low Current
IDT
™
/ ICS
™
LVPECL FREQUENCY MARGINING SYNTHESIZER
4
ICS843207CY-350 REV. A JANUARY 16, 2008
ICS843207-350
FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER
T
ABLE
5C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3.3V±5%, V
EE
=
O
V, T
A
= 0°C
TO
70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CCO
- 1.4
V
CCO
- 2.0
0.6
Typical
Maximum
V
CCO
- 0.9
V
CCO
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
CCO
- 2V.
T
ABLE
6. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
NOTE: Characterized using an 18pF parallel resonant cr ystal.
12.4
Test Conditions
Minimum
Typical Maximum
14
15
40
7
300
Units
MHz
Ω
pF
µW
Fundamental
T
ABLE
7. AC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3.3V±5%, V
EE
=
O
V, T
A
= 0°C
TO
70°C
Symbol
f
OUT
f
IN
Parameter
Output Frequency
Input Frequency
REF_CLK
Mode = LOW
350MHz, (12kHz - 20MHz)
Mode = LOW
175MHz, (12kHz - 20MHz)
Mode = LOW
87.5MHz, (12kHz - 20MHz)
20% to 80%
Output Divider = ÷2
Output Divider =
≠2
Test Conditions
N = ÷2
N = ÷4
N = ÷8
Minimum
310
155
77.5
12.4
Typical
350
175
87.5
14
1.54
1.48
1.61
300
42
46
600
58
64
Maximum
375
187.5
93.75
15
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
%
%
t
jit(Ø)
RMS Phase Jitter, Random;
NOTE 1
t
R
/ t
F
odc
Output Rise/Fall Time
Output Duty Cycle
NOTE 1: Characterized using a 14MHz cr ystal.
IDT
™
/ ICS
™
LVPECL FREQUENCY MARGINING SYNTHESIZER
5
ICS843207CY-350 REV. A JANUARY 16, 2008
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