K7N803645B
K7N801845B
256Kx36 & 512Kx18 Pipelined NtRAM
TM
8Mb NtRAM
TM
Specification
100 TQFP with Pb & Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-
lar applications where Product failure couldresult in loss of life or personal or physical harm, or any military
or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
-1-
Rev. 5.0 April 2006
K7N803645B
K7N801845B
Document Title
256Kx36 & 512Kx18 Pipelined NtRAM
TM
256Kx36 & 512Kx18-Bit Pipelined NtRAM
TM
Revision History
Rev. No.
0.0
0.1
0.2
1.0
History
1. Initial document.
1. Add x32 org part and industrial temperature part
1. change scan order(1) form 4T to 6T at 119BGA(x18)
1. Final spec release
2. Change I
SB1
form 80mA to 100mA
3. Change I
SB2
form 40mA to 60mA
Change ordering information( remove 225MHz at Nt-Pipelined)
1. Delete 119BGA package
1. Remove x32 organization
1. Add the overshoot timing
1. Change ordering information
Draft Date
May. 18. 2001
Aug. 11. 2001
Aug. 28. 2001
Nov. 16. 2001
Remark
Preliminary
Preliminary
Preliminary
Final
2.0
2.1
3.0
4.0
5.0
April. 01. 2002
April. 04. 2003
Nov. 17. 2003
Feb. 16. 2006
Apr. 03. 2006
Final
Final
Final
Final
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-2-
Rev. 5.0 April 2006
K7N803645B
K7N801845B
256Kx36 & 512Kx18 Pipelined NtRAM
TM
8Mb NtRAM(Flow Through / Pipelined) Ordering Information
Org.
512Kx18
256Kx36
VDD (V)
2.5
2.5
2.5
2.5
Speed (ns)
6.0
7.5
6.0
7.5
Access Time (ns)
3.5
4.2
3.5
4.2
Part Number
K7N801845B-P(Q)
1
C(I)
2
16
K7N801845B-Q
3
C(I)13
K7N803645B-P(Q)
1
C(I)
2
16
K7N803645B-Q
3
C(I)13
RoHS Avail.
√
•
√
•
Note 1. P(Q) [Package type] : P-Pb Free, Q-Pb
2. C(I) [Operating Temperature] : C-Commercial, I-Industrial
3. Support only Pb package Parts. For Pb-Free package, use faster frequency parts.
-3-
Rev. 5.0 April 2006
K7N803645B
K7N801845B
256Kx36 & 512Kx18 Pipelined NtRAM
TM
256Kx36 & 512Kx18-Bit Pipelined NtRAM
TM
FEATURES
• 2.5V
±5%
Power Supply.
• Byte Writable Function.
• Enable clock and suspend operation.
• Single READ/WRITE control pin.
• Self-Timed Write Cycle.
• Three Chip Enable for simple depth expansion with no data
contention .
•
Α
interleaved burst or a linear burst mode.
• Asynchronous output enable control.
• Power Down mode.
• TTL-Level Three-State Outputs.
•100-TQFP-1420A
• Operating in commeical and industrial temperature range.
GENERAL DESCRIPTION
The K7N803645B and K7N801845B are 9,437,184 bits Syn-
chronous Static SRAMs.
The NtRAM
TM
, or No Turnaround Random Access Memory
utilizes all the bandwidth in any combination of operating
cycles.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation
and provides increased timing flexibility for incoming signals.
For read cycles, pipelined SRAM output data is temporarily
stored by an edge triggered output register and then released
to the output buffers at the next rising edge of clock.
The K7N803645B and K7N801845B are implemented with
SAMSUNG′s high performance CMOS technology and is
available in 100pin TQFP and Multiple power and ground pins
minimize ground bounce.
FAST ACCESS TIMES
PARAMETER
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol
t
CYC
t
CD
t
OE
-16
6.0
3.5
3.5
-13
7.5
4.2
3.8
Unit
ns
ns
ns
LOGIC BLOCK DIAGRAM
A [0:17]or
A [0:18]
LBO
ADDRESS
REGISTER
A
2
~A
17
or A
2
~A
18
A
0
~A
1
BURST
ADDRESS
COUNTER
A′
0
~A′
1
256Kx36 , 512Kx18
MEMORY
ARRAY
CLK
CKE
K
WRITE
ADDRESS
REGISTER
WRITE
ADDRESS
REGISTER
CONTROL
LOGIC
K
DATA-IN
REGISTER
DATA-IN
REGISTER
K
CS
1
CS
2
CS
2
ADV
WE
BW
x
(x=a,b,c,d or a,b)
OE
ZZ
DQa
0
~ DQd
7
or DQa
0
~ DQb
8
DQPa ~ DQPd
36 or 18
CONTROL
REGISTER
CONTROL
LOGIC
K
OUTPUT
REGISTER
BUFFER
NtRAM
TM
and No Turnaround Random Access Memory are trademarks of Samsung,
and its architecture and functionalities are supported by NEC and Toshiba.
-4-
Rev. 5.0 April 2006
K7N803645B
K7N801845B
PIN CONFIGURATION
(TOP VIEW)
BWd
BWb
256Kx36 & 512Kx18 Pipelined NtRAM
TM
BWa
BWc
CKE
ADV
N.C.
CLK
CS
1
CS
2
CS
2
V
DD
V
SS
WE
A
6
A
17
83
OE
A
7
A
8
82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
81
A
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
N.C.
N.C.
N.C.
N.C.
V
SS
A
5
A
4
A
3
A
2
A
1
A
0
A
10
A
12
A
13
A
14
A
15
LBO
V
DD
PIN NAME
SYMBOL
A
0
- A
17
PIN NAME
Address Inputs
TQFP PIN NO.
32,33,34,35,36,37,
44,45,46,47,48,49,
50,81,82,83,99,100
85
88
89
87
98
97
92
93,94,95,96
86
64
31
SYMBOL
V
DD
V
SS
N.C.
DQa
0
~a
7
DQb
0
~b
7
DQc
0
~c
7
DQd
0
~d
7
DQPa~P
d
V
DDQ
V
SSQ
PIN NAME
Power Supply(+2.5V)
Ground
No Connect
Data Inputs/Outputs
TQFP PIN NO.
14,15,16,41,65,66,91
17,40,67,90
38,39,42,43,84
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
ADV
WE
CLK
CKE
CS
1
CS
2
CS
2
BWx
OE
ZZ
LBO
Address Advance/Load
Read/Write Control Input
Clock
Clock Enable
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Power Sleep Mode
Burst Mode Control
Notes :
1. The pin 84 is reserved for address bit for the 16Mb NtRAM.
2. A
0
and A
1
are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
A
11
Output Power Supply
(+2.5V)
Output Ground
A
16
50
DQPc
DQc
0
DQc
1
V
DDQ
V
SSQ
DQc
2
DQc
3
DQc
4
DQc
5
V
SSQ
V
DDQ
DQc
6
DQc
7
V
DD
V
DD
V
DD
V
SS
DQd
0
DQd
1
V
DDQ
V
SSQ
DQd
2
DQd
3
DQd
4
DQd
5
V
SSQ
V
DDQ
DQd
6
DQd
7
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
K7N803645B(256Kx36)
DQPb
DQb
7
DQb
6
V
DDQ
V
SSQ
DQb
5
DQb
4
DQb
3
DQb
2
V
SSQ
V
DDQ
DQb
1
DQb
0
V
SS
V
DD
V
DD
ZZ
DQa
7
DQa
6
V
DDQ
V
SSQ
DQa
5
DQa
4
DQa
3
DQa
2
V
SSQ
V
DDQ
DQa
1
DQa
0
DQPa
-5-
Rev. 5.0 April 2006
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