Integrated
Circuit
Systems, Inc.
ICS83905I
L
OW
S
KEW
, 1:6 C
RYSTAL
I
NTERFACE
-
TO
-
LVCMOS / LVTTL F
ANOUT
B
UFFER
F
EATURES
•
6 LVCMOS / LVTTL outputs
•
Outputs able to drive 12 series terminated lines
•
Crystal oscillator interface
•
Crystal input frequency range: 10MHz to 40MHz
•
Output skew: 80ps (maximum)
•
RMS phase jitter @ 25MHz, (100Hz - 1MHz):
0.26ps (typical) (V
DD
= V
DDO
= 2.5V)
Phase noise:
Offset
Noise Power
100Hz .............. -129.7 dBc/Hz
1kHz .............. -144.4 dBc/Hz
10kHz .............. -147.3 dBc/Hz
100kHz .............. -157.3 dBc/Hz
•
5V tolerant enable inputs
•
Synchronous output enables
•
Operating power supply modes:
Full 3.3V, 2.5V and 1.8V,
mixed 3.3V core/2.5V output operating supply,
mixed 3.3V core/1.8V output operating supply,
mixed 2.5V core/1.8V output operating supply
•
-40°C to 85°C ambient operating temperature
•
Lead-Free package fully RoHS compliant
G
ENERAL
D
ESCRIPTION
The ICS83905I is a low skew, 1-to-6 LVCMOS /
LVTTL Fanout Buffer and a member of the
HiPerClockS™
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The low impedance
LVCMOS/LVTTL outputs are designed to drive
50W series or parallel terminated transmission lines. The ef-
fective fanout can be increased from 6 to 12 by utilizing the
ability of the outputs to drive two series terminated lines.
ICS
The ICS83905I is characterized at full 3.3V, 2.5V, and 1.8V,
mixed 3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating
supply mode. Guaranteed output and part-to-part skew
characteristics along with the 1.8V output capabilities makes
the ICS83905I ideal for high performance, single ended appli-
cations that also require a limited output voltage.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
BCLK0
XTAL_OUT
ENABLE 2
GND
BCLK0
V
DD
o
BCLK1
GND
BCLK2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
XTAL_IN
ENABLE 1
BCLK5
V
DDO
BCLK4
GND
BCLK3
V
DD
BCLK1
XTAL_IN
BCLK2
XTAL_OUT
ICS83905I
BCLK3
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm body package
G Pacakge
Top View
BCLK4
ENABLE 1
SYNCHRONIZE
BCLK5
ENABLE 2
SYNCHRONIZE
83905AGI
http://www.icst.com/products/hiperclocks.html
1
REV. B MAY 16, 2005
Integrated
Circuit
Systems, Inc.
ICS83905I
L
OW
S
KEW
, 1:6 C
RYSTAL
I
NTERFACE
-
TO
-
LVCMOS / LVTTL F
ANOUT
B
UFFER
Type
Output
Input
Power
Output
Power
Power
Input
Description
Crystal oscillator interface. XTAL_OUT is the output.
Clock enable. LVCMOS / LVTTL interface levels. See Table 3.
Power supply ground.
Clock outputs. LVCMOS / LVTTL interface levels.
Output supply pin.
Core supply pin.
Crystal oscillator interface. XTAL_IN is the input.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2 , 15
3, 7, 11
4, 6, 8,
10, 12, 14
5, 13
9
16
Name
XTAL_OUT
ENABLE 2, ENABLE 1
GND
BCLK0, BCLK1, BCLK2,
BCLK3, BCLK4, BCLK5
V
DDO
V
DD
XTAL_IN
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
V
DDO
= 3.465V
V
DDO
= 2.625V
V
DDO
= 2V
V
DDO
= 3.3V ± 5%
R
OUT
Output Impedance
V
DDO
= 2.5V ± 5%
V
DDO
= 1.8V ± 0.2V
7
7
10
Test Conditions
Minimum
Typical
4
19
18
16
Maximum
Units
pF
pF
pF
pF
Ω
Ω
Ω
T
ABLE
3. O
UTPUT
E
NABLE
Control Inputs
ENABLE 1
0
0
1
1
AND
C
LOCK
E
NABLE
F
UNCTION
T
ABLE
Outputs
BCLK0:BCLK4
LOW
LOW
Toggling
Toggling
BCLK5
LOW
Toggling
LOW
Toggling
ENABLE 2
0
1
0
1
BCLK5
BCLK0:4
ENABLE2
ENABLE1
F
IGURE
1. E
NABLE
T
IMING
D
IAGRAM
83905AGI
http://www.icst.com/products/hiperclocks.html
2
REV. B MAY 16, 2005
Integrated
Circuit
Systems, Inc.
ICS83905I
L
OW
S
KEW
, 1:6 C
RYSTAL
I
NTERFACE
-
TO
-
LVCMOS / LVTTL F
ANOUT
B
UFFER
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
89°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
16 Lead TSSOP package
Storage Temperature, T
STG
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
ENABLE 1:2 = 00
ENABLE 1:2 = 00
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
10
5
Units
V
V
mA
mA
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
ENABLE 1:2 = 00
ENABLE 1:2 = 00
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
8
4
Units
V
V
mA
mA
T
ABLE
4C. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
ENABLE 1:2 = 00
ENABLE 1:2 = 00
Test Conditions
Minimum
1.6
1.6
Typical
1.8
1.8
Maximum
2.0
2.0
5
3
Units
V
V
mA
mA
T
ABLE
4D. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
ENABLE 1:2 = 00
ENABLE 1:2 = 00
Test Conditions
Minimum
3.135
2.375
Typical
3.3
2.5
Maximum
3.465
2.625
10
4
Units
V
V
mA
mA
83905AGI
http://www.icst.com/products/hiperclocks.html
3
REV. B MAY 16, 2005
Integrated
Circuit
Systems, Inc.
ICS83905I
L
OW
S
KEW
, 1:6 C
RYSTAL
I
NTERFACE
-
TO
-
LVCMOS / LVTTL F
ANOUT
B
UFFER
Test Conditions
Minimum
3.135
1.6
ENABLE 1:2 = 00
ENABLE 1:2 = 00
Typical
3.3
1.8
Maximum
3.465
2.0
10
3
Units
V
V
mA
mA
T
ABLE
4E. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
T
ABLE
4F. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 2.5V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
ENABLE 1:2 = 00
ENABLE 1:2 = 00
Test Conditions
Minimum
2.375
1.6
Typical
2.5
1.8
Maximum
2.625
2.0
8
3
Units
V
V
mA
mA
T
ABLE
4G. LVCMOS/LVTTL DC C
HARACTERISTICS
,
T
A
= -40°C
TO
85°C
Symbol
V
IH
Parameter
Input High Voltage
ENABLE 1,
ENABLE 2
Test Conditions
V
DD
= 3.3V ± 5%
V
DD
= 2.5V ± 5%
V
DD
= 1.8V ± 0.2V
V
IL
Input Low Voltage
ENABLE 1,
ENABLE 2
V
DD
= 3.3V ± 5%
V
DD
= 2.5V ± 5%
V
DD
= 1.8V ± 0.2V
V
DDO
= 3.3V ± 5%; NOTE 1
V
OH
Output High Voltage
V
DDO
= 2.5V ± 5%; I
OH
= -1mA
V
DDO
= 2.5V ± 5%; NOTE 1
V
DDO
= 1.8V ± 0.2V; NOTE 1
V
DDO
= 3.3V ± 5%; NOTE 1
V
OL
Output Low Voltage
V
DDO
= 2.5V ± 5%; I
OL
= 1mA
V
DDO
= 2.5V ± 5%; NOTE 1
V
DDO
= 1.8V ± 0.2V; NOTE 1
Minimum
2
1.7
0.65*V
DD
-0.3
-0.3
-0.3
2.6
2
1.8
V
DDO
- 0.3
0.5
0.4
0.45
0.35
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
0.35*V
DD
Units
V
V
V
V
V
V
V
V
V
V
V
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
DDO
/2. See Parameter Measurement section, "Load Test Circuit" diagrams.
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
http://www.icst.com/products/hiperclocks.html
4
Test Conditions
Minimum
10
Typical
Fundamental
Maximum
40
50
7
1
Units
MHz
Ω
pF
mW
83905AGI
REV. B MAY 16, 2005
Integrated
Circuit
Systems, Inc.
ICS83905I
L
OW
S
KEW
, 1:6 C
RYSTAL
I
NTERFACE
-
TO
-
LVCMOS / LVTTL F
ANOUT
B
UFFER
Test Conditions
Using External Crystal
Minimum Typical Maximum Units
10
DC
48
40
100
52
80
25MHz @ (Integration
Range: 100Hz-1MHz)
20% to 80%
ENABLE 1
ENABLE 2
200
0.13
800
4
4
4
4
MHz
MHz
%
ps
ps
ps
cycles
cycles
cycles
cycles
T
ABLE
6A. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol Parameter
f
MAX
odc
Output Frequency
Output Duty Cycle
Output Skew; NOTE 2, 4
RMS Phase Jitter (Random)
Output Rise/Fall Time
Output Enable Time;
NOTE 3
Using External Clock
Source; NOTE 1
t
sk(o)
t
jit(Ø)
t
R
/t
F
t
EN
t
DIS
Output Disable Time; ENABLE 1
NOTE 3
ENABLE 2
All parameters measured at ƒ
≤
f
MAX
using a crystal input unless noted otherwise.
Terminated at 50
Ω
to V
DDO
/2.
NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
6B. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol Parameter
Using External Crystal
f
MAX
odc
Output Frequency
Output Duty Cycle
Output Skew; NOTE 2, 5
RMS Phase Jitter (Random); NOTE 3
Output Rise/Fall Time
Output Enable Time;
NOTE 4
ENABLE 1
ENABLE 2
25MHz @ (Integration
Range: 100Hz-1MHz)
20% to 80%
200
0.26
800
4
4
4
4
Using External Clock
Source; NOTE 1
Test Conditions
Minimum Typical Maximum Units
10
DC
47
40
100
53
80
MHz
MHz
%
ps
ps
ps
cycles
cycles
cycles
cycles
t
sk(o)
t
jit(Ø)
t
R
/t
F
t
EN
t
DIS
Output Disable Time; ENABLE 1
NOTE 4
ENABLE 2
All parameters measured at ƒ
≤
f
MAX
using a crystal input unless noted otherwise.
Terminated at 50
Ω
to V
DDO
/2.
NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 3: Please refer to phase noise plot.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
83905AGI
http://www.icst.com/products/hiperclocks.html
5
REV. B MAY 16, 2005
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