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6-Bit Programmable 2-/3-Phase
Synchronous Buck Controller
ADP3197
FEATURES
Selectable 2-phase and 3-phase operation at up to 1 MHz
per phase
±10 mV worst-case differential sensing error over
temperature
Logic-level PWM outputs for interface to external high
power drivers
Enhanced PWM flex mode for excellent load transient
performance
Active current balancing between all output phases
Built-in power good/crowbar blanking that supports
on-the-fly VID code changes
Digitally programmable 0.3750 V to 1.55 V output
Programmable short-circuit protection with
programmable latch-off delay
FUNCTIONAL BLOCK DIAGRAM
VCC
24
RT
9
RAMPADJ
10
SHUNT
REGULATOR
OSCILLATOR
SET
GND 15
EN
16 OD
UVLO
SHUTDOWN
800mV
EN
1
–
+
CURRENT
BALANCING
CIRCUIT
+
CMP
–
+
CMP
–
+
CMP
–
RESET
23 PWM1
2.2V
CSREF
–
+
RESET
2-/3-PHASE
DRIVER LOGIC
RESET
22 PWM2
+
DAC – 250mV
–
21 PWM3
CURRENT
LIMIT
PWRGD
2
DELAY
CROWBAR
20 SW1
TTSENSE 31
19 SW2
THERMAL
THROTTLING
CONTROL
18 SW3
APPLICATIONS
Desktop PC power supplies for
Next-generation AMD processors
Voltage regulator modules (VRM)
VRHOT
32
14 CSCOMP
ILIMIT
DELAY
8
7
CURRENT
MEASUREMENT
AND LIMIT
+
–
13 CSSUM
12 CSREF
GENERAL DESCRIPTION
The ADP3197
1
is a highly efficient multiphase synchronous buck
switching regulator controller optimized for converting a 12 V
main supply into the core supply voltage required by high perform-
ance, Advanced Micro Devices, AMD processors. It uses an
internal 6-bit digital-to-analog converter (DAC) to read a voltage
identification (VID) code directly from the processor, which is
used to set the output voltage between 0.3750 V and 1.55 V. It uses
a multimode pulse-width modulation (PWM) architecture to
drive the logic level outputs at a programmable switching
frequency that can be optimized for VR size and efficiency.
The phase relationship of the output signals can be programmed
to provide 2-phase or 3-phase operation, allowing for the
construction of up to three complementary buck switching stages.
The ADP3197 supports a programmable slope function to adjust
the output voltage as a function of the load current so it is always
optimally positioned for a system transient. This can be disabled
by connecting the LLSET pin to the CSREF pin.
The ADP3197 also provides accurate and reliable short-circuit
protection, adjustable current limiting, and a delayed power-
good output that accommodates on-the-fly output voltage
changes requested by the CPU.
1
IREF 17
COMP
5
PRECISION
REFERENCE
FBRTN
3
SOFT START
CONTROL
–
+
+
–
4 FB
11 LLSET
6 SS
VID DAC
ADP3197
25
26
27
VID3
28
VID2
29
VID1
30
VID0
VID5 VID4
Figure 1.
The ADP3197 has a built-in shunt regulator that allows the part
to be connected to the 12 V system supply through a series resistor.
The ADP3197 is specified over the extended commercial tempera-
ture range of 0°C to 85°C and is available in a 32-lead LFCSP.
Protected by U.S. Patent Number 6,683,441; other patents pending.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
06668-001
ADP3197
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 8
Test Circuits....................................................................................... 9
Theory of Operation ...................................................................... 10
Start-Up Sequence...................................................................... 10
Phase Detection Sequence......................................................... 10
Master Clock Frequency............................................................ 11
Output Voltage Differential Sensing ........................................ 11
Output Current Sensing ............................................................ 11
Active Impedance Control Mode............................................. 11
Current Control Mode and Thermal Balance ........................ 11
Voltage Control Mode................................................................ 12
Current Reference ...................................................................... 12
Enhanced PWM Mode .............................................................. 12
Delay Timer................................................................................. 12
Soft Start ...................................................................................... 12
Current Limit, Short-Circuit, and Latch-Off Protection ...... 13
Dynamic VID.............................................................................. 13
Power-Good Monitoring........................................................... 13
Output Crowbar ......................................................................... 14
Output Enable and UVLO ........................................................ 14
Thermal Monitoring .................................................................. 14
Typical Application Circuit....................................................... 16
Applications Information .............................................................. 17
Setting the Clock Frequency..................................................... 17
Soft Start Delay Time................................................................. 17
Current-Limit Latch-Off Delay Times .................................... 17
Inductor Selection ...................................................................... 18
Current Sense Amplifier............................................................ 18
Inductor DCR Temperature Correction ................................. 19
Output Offset .............................................................................. 20
C
OUT
Selection ............................................................................. 20
Power MOSFETs......................................................................... 21
Ramp Resistor Selection............................................................ 22
COMP Pin Ramp ....................................................................... 23
Current-Limit Setpoint.............................................................. 23
Feedback Loop Compensation Design.................................... 23
C
IN
Selection and Input Current di/dt Reduction.................. 25
Thermal Monitor Design .......................................................... 25
Shunt Resistor Design................................................................ 25
Tuning the ADP3197 ................................................................. 26
Layout and Component Placement ......................................... 27
Outline Dimensions ....................................................................... 29
Ordering Guide .......................................................................... 29
REVISION HISTORY
5/07—Revision
0: Initial Version
Rev. 0 | Page 2 of 32
ADP3197
SPECIFICATIONS
VCC = 5 V, FBRTN = GND, T
A
= 0°C to 85°C, unless otherwise noted
1
Table 1.
Parameter
REFERENCE CURRENT
Reference Bias Voltage
Reference Bias Current
ERROR AMPLIFIER
Output Voltage Range
2
Accuracy
Load Line Positioning Accuracy
Differential Nonlinearity
Input Bias Current
FBRTN Current
Output Current
Gain Bandwidth Product
Slew Rate
LLSET Input Voltage Range
LLSET Input Bias Current
VID INPUTS
Input Low Voltage
Input High Voltage
Input Current
VID Transition Delay Time
2
OSCILLATOR
Frequency Range
2
Frequency Variation
Symbol
V
IREF
I
IREF
V
COMP
V
FB
Conditions
Min
Typ
1.5
15
Max
Unit
V
μA
V
mV
mV
LSB
μA
μA
μA
MHz
V/μs
mV
nA
V
V
μA
ns
MHz
kHz
kHz
kHz
V
mV
μA
mV
nA
MHz
V/μs
V
V
μA
ms
mV
kΩ
μA
%
μA
V
R
IREF
= 100 kΩ
14.25
0.05
−10
−78
−1
−9
15.75
4.4
10
Relative to nominal DAC output, referenced to FBRTN,
LLSET = CSREF (see Figure 4)
CSREF – LLSET = 80 mV
I
FB
= 0.5 × I
IREF
FB forced to V
OUT
– 3%
COMP = FB
COMP = FB
Relative to CSREF
−80
−7.5
65
500
20
25
I
FB
I
FBRTN
I
COMP
GBW
(ERR)
V
LLSET
I
LLSET
V
IL(VID)
V
IH(VID)
I
IN(VID)
−82
+1
−6
200
−250
−10
+250
+10
0.6
VIDx, VIDSEL
VIDx, VIDSEL
VID code change to FB change
1.4
−10
400
0.25
180
3
220
f
OSC
f
PHASE
Output Voltage
RAMPADJ Output Voltage
RAMPADJ Input Current Range
CURRENT SENSE AMPLIFIER
Offset Voltage
Input Bias Current
Gain Bandwidth Product
Slew Rate
Input Common-Mode Range
Output Voltage Range
Output Current
Current Limit Latch-off Delay Time
CURRENT BALANCE AMPLIFIER
Common-Mode Range
Input Resistance
Input Current
Input Current Matching
CURRENT LIMIT COMPARATOR
ILIMIT Bias Current
ILIMIT Voltage
V
RT
V
RAMPADJ
I
RAMPADJ
V
OS(CSA)
I
BIAS(CSSUM)
GBW
(CSA)
T
A
= 25°C, R
T
= 280 kΩ, 3-phase
T
A
= 25°C, R
T
= 130 kΩ, 3-phase
T
A
= 25°C, R
T
= 57.6 kΩ, 3-phase
R
T
= 280 kΩ to GND
RAMPADJ − FB, DAC=1.55 V
1.9
−50
1
−1.0
−10
200
400
800
2.0
2.1
+50
50
+1.0
+10
CSSUM – CSREF (see Figure 5)
CSSUM = CSCOMP
C
CSCOMP
= 10 pF
CSSUM and CSREF
10
10
0
0.05
500
8
−600
10
8
−4
9
1.09
+200
26
20
+4
11
1.33
3.5
3.5
I
CSCOMP
t
OC(DELAY)
V
SWxCM
R
SWx
I
SWx
ΔI
SWx
I
ILIMIT
V
ILIMIT
C
DELAY
= 10 nF
SWx = 0 V
SWx = 0 V
SWx = 0 V
I
ILIMIT
= 2/3 × I
IREF
R
ILIMIT
= 121 kΩ (V
ILIMIT
= I
ILIMIT
× R
ILIMIT
)
17
12
10
1.21
Rev. 0 | Page 3 of 32
ADP3197
Parameter
Maximum Output Voltage
Current Limit Threshold Voltage
Current Limit Setting Ratio
DELAY TIMER
Normal Mode Output Current
Output Current in Current Limit
Threshold Voltage
SOFT START
Output Current (Startup)
Output Current (DAC Code Change)
ENABLE INPUT
Threshold Voltage
Hysteresis
Input Current
Delay Time
OD OUTPUT
Output Low Voltage
Output High Voltage
OD Pulldown Resistor
THERMAL THROTTLING CONTROL
TTSENSE Voltage Range
TTSENSE Bias Current
TTSENSE VRHOT Threshold
Voltage
TTSENSE Hysteresis
VRHOT Output Low Voltage
POWER-GOOD COMPARATOR
Overvoltage Threshold
Undervoltage Threshold
Output Low Voltage
Power-Good Delay Time
During Soft Start
2
VID Code Changing
VID Code Static
Crowbar Trip Point
Crowbar Reset Point
PWM OUTPUTS
Output Low Voltage
Output High Voltage
SUPPLY
VCC
DC Supply Current
UVLO Turn On Current
UVLO Threshold Voltage
UVLO Threshold Voltage
1
2
Symbol
V
CL
Conditions
V
CSREF
− V
CSCOMP
, R
ILIMIT
= 121 kΩ
V
CL
/I
ILIMIT
I
DELAY
= I
IREF
I
DELAY(CL)
= 0.25 × I
IREF
Min
3
80
Typ
100
82.6
15
3.75
1.7
3.75
18.75
800
100
−1
2
160
Max
125
Unit
V
mV
mV/V
μA
μA
V
μA
μA
mV
mV
μA
ms
mV
V
kΩ
I
DELAY
I
DELAY(CL)
V
DELAY(TH)
I
SS(STARTUP)
I
SS(DAC)
V
TH(EN)
V
HYS(EN)
I
IN(EN)
t
DELAY(EN)
V
OL(OD)
V
OH(OD)
12
3.0
1.6
3
15
750
80
18
4.5
1.8
4.5
22.5
850
125
During startup, I
SS(STARTUP)
= 0.25 × I
IREF
DAC code change, I
SS(DAC)
= 1.25 × I
IREF
EN > 950 mV, C
DELAY
= 10 nF
500
4
5
60
Internally limited
0
−135
665
−123
710
50
150
5
−111
755
V
μA
mV
mV
mV
mV
mV
mV
mV
mV
ms
μs
ns
V
mV
mV
V
V
mA
mA
V
V
OL(VRHOT)
V
PWRGD(OV)
V
PWRGD(UV)
V
OL(PWRGD)
I
VRHOT(SINK)
= −4 mA
Relative to nominal DAC output; DAC = 0.5 V to 1.55 V
Relative to nominal DAC output; DAC = 0.375 V to 0.4785 V
Relative to nominal DAC output; DAC = 0.5 V to 1.55 V
Relative to nominal DAC output; DAC = 0.375 V to 0.4785 V
I
PWRGD(SINK)
= −4 mA
C
DELAY
= 10 nF
100
200
190
−300
−310
300
300
310
−200
−190
300
250
250
−250
−250
150
2
250
200
1.8
300
160
5
5
6.5
V
CROWBAR
Relative to FBRTN
Relative to FBRTN
I
PWM(SINK)
= −400 μA
I
PWM(SOURCE)
= +400 μA
V
SYSTEM
= 12 V, R
SHUNT
= 340 Ω (see Figure 4)
1.75
1.85
V
OL(PWM)
V
OH(PWM)
VCC
I
VCC
V
UVLO
V
UVLO
500
4.0
4.65
5.55
25
11
VCC rising
VCC falling
9
4.1
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
Guaranteed by design or bench characterization; not tested in production.
Rev. 0 | Page 4 of 32
Analogue and Mixed Signal
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