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FEATURES
Personal System/2* and VGA* Compatible
Plug-in Replacement for INMOS 171/176
66 MHz Pipelined Operation
Three 6-Bit D/A Converters
256 18 Color Palette RAM
RS-343A/RS-170 Compatible Outputs
Blank on All Three Channels
Standard MPU Interface
Asynchronous Access to All Internal Registers
5 V CMOS Monolithic Construction
Low Power Dissipation
Standard 28-Pin, 0.6" DIP and 44-Pin PLCC
APPLICATIONS
High Resolution Color Graphics
CAE/CAD/CAM Applications
Image Processing
Instrumentation
Desktop Publishing
AVAILABLE CLOCK RATES
66 MHz
50 MHz
35 MHz
GENERAL DESCRIPTION
®
CMOS Monolithic 256 18
Color Palette RAM-DAC
ADV476
FUNCTIONAL BLOCK DIAGRAM
OBS
The ADV476 (ADV ) is a pin compatible and software compat-
ible RAM-DAC designed specifically for VGA and Personal
System/2 color graphics.
The ADV476 is a complete analog output RAM-DAC on a
single monolithic chip. The part contains a 256 18 color
lookup table, a pixel mask register as well as a triple 6-bit video
D/A converter. The ADV476 is capable of simultaneously dis-
playing up to 256 colors, from a total color palette of 262,144
addressable colors.
The on-chip asynchronous MPU bus allows access to the color
lookup table without affecting the input video data via the pixel
port. The pixel read mask register provides a convenient way of
altering the displayed colors without updating the color lookup
table. The ADV476 is capable of generating RGB video output
signals which are compatible with RS-343A and RS-170 video
standards, without requiring external buffering.
OLE
TE
PRODUCT HIGHLIGHTS
The ADV476 is fabricated in a +5 V CMOS process. Its mono-
lithic CMOS construction ensures greater functionality with low
power dissipation and small board area. The part is packaged in
a 0.6", 28-pin DIP and a 44-pin PLCC.
1. Standard video refresh rates, 35 MHz, 50 MHz and
66 MHz.
2. Fully compatible with VGA and Personal System/2 color
graphics.
3. Guaranteed monotonic. Integral and differential linearity
guaranteed to be a maximum of
±
1 LSB.
4. Low glitch energy, 75 pV secs.
*Personal
System/2 and VGA are trademarks of International Business
Machines Corp.
ADV is a registered trademark of Analog Devices, Inc.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
ADV476–SPECIFICATIONS
Parameter
STATIC PERFORMANCE
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity
Full Scale Error
Blank Level
Offset Error
DIGITAL INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Current (RD Input Only)
Input Capacitance, C
IN
6
±
0.5
±
5
±
0.5
±
0.5
2
0.8
±
10
±
100
7
(V
CC
= +5 V 10%, I
REF
= 8.88 mA.
All Specifications T
MIN
to T
MAX1
unless otherwise noted.)
Units
Bits
LSB max
% max
LSB max
LSB max
V min
V max
µA
max
µA
max
pF typ
V min
V max
µA
max
pF typ
Guaranteed Monotonic
Full Scale = 2.15 I
REF
BLANK
= Logic Low
BLANK
= Logic High
Test Conditions/Comments
All Versions
R
L
, I
REF
= 8.39 mA
OBS
DIGITAL OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
2.4
0.4
±
50
7
ANALOG OUTPUTS
Max Output Voltage
Max Output Current
DAC to DAC Matching
2
Analog Output Capacitance
CURRENT REFERENCE
Input Current (I
REF
) Range
Voltage at I
REF
POWER SUPPLY
Supply Voltage, V
CC
Supply Current, I
CC
Power Supply Rejection Ratio
DYNAMIC PERFORMANCE
Clock and Data Feedthrough
3, 4
Glitch Impulse
3, 4
1.5
21
±
2.5
10
4.5/5.5
220
6
–35
75
Specifications subject to change without notice.
V
CC
= 5.5 V, V
IN
= 0.4 V to V
CC
V
CC
= 5.5 V, V
IN
= 0.4 V to V
CC
–3/–10
V
CC
–3/V
CC
OLE
TE
V min
mA min
% max
pF typ
IO < 10 mA, IO = 2.15
VO
≤
1 V
BLANK
= Logic Low
I
REF
mA min/mA max
V min/V max
V min/V max
mA max
%/V
I
REF
= 8.88 mA
f
MAX
= 66 MHz IO = 2.15 I
REF
, D0–D7 Unloaded
4.5 < V
CC
< 5.5 V, IO = 2.15 I
REF
, R
L
= 37.5
Ω,
C
L
= 30 pF, I
REF
= 8.88 mA.
dB typ
pV secs typ
I
SOURCE
= 500
µA,
V
CC
= 4.5 V
I
SINK
= 5.0 mA, V
CC
= 4.5 V
V
CC
= 5.5 V, 0.4 V < V
IN
< V
CC
NOTES
1
Temperature range (T
MIN
to T
MAX
); 0 to +70°C.
2
Relative to the midpoint of the distribution of the three DACs measured at full scale.
3
TTL input values are 0 to 3 volts, with input rise/fall times
≤3
ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and out-
puts. Analog output load
≤10
pF, 37.5
Ω.
D0–D7 output load
≤50
pF. See timing notes in Figure 2.
4
Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. For this test, the digital inputs have a 1 k
Ω
resistor to
ground and are driven by 74HC logic. Glitch impulse includes clock and data feedthrough, –3 dB test bandwidth = 2 clock rate.
–2–
REV. B
ADV476
TIMING CHARACTERISTICS
1
(V
Parameter
f
MAX
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
173
t
18
t
PD
66 MHz Version
66
10
10
5
40
20
10
10
50
4 t
12
3
3
15.3
5
5
30
5
6
15.3
2
4
CC
= +5 V
10%. All Specifications T
MIN
to T
MAX2
)
35 MHz Version
35
15
15
5
40
20
15
15
50
4 t
12
4
4
28
7
9
30
5
8
25
2
4
Units
MHz
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns typ
ns min
clocks
Conditions/Comments
Clock Rate
RS0, RS1 Setup Time
RS0, RS1 Hold Time
RD
Asserted to Data Bus Driven
RD
Asserted to Data Valid
RD
Negated to Data Bus 3-Stated
Write Data Setup Time
Write Data Hold Time
RD, WR
Pulse Width Low
RD, WR
Pulse Width High
Pixel & Control Setup Time
Pixel & Control Hold Time
Clock Cycle Time
Clock Pulse Width High Time
Clock Pulse Width Low Time
Analog Output Delay
50 MHz Version
50
10
10
5
40
20
10
10
50
4 t
12
3
3
20
6
6
30
5
8
20
2
4
OBS
Specifications subject to change without notice.
NOTES
1
TTL input values are 0 to 3 volts, with input rise/fall times
≤3
ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. Analog output load
≤10
pF, 37.5
Ω.
D0–D7 output load
≤50
pF. See timing notes in Figure 2.
2
Temperature Range (T
MIN
to T
MAX
); 0 to +70°C
3
Settling time does not include clock and data feedthrough. For this test, the digital inputs have a 1 k
Ω
resistor to ground and are driven by 74HC logic.
OLE
TE
Analog Output Rise/Fall Time
Analog Output Settling Time
Analog Output Skew
Pipeline Delay
Figure 1. MPU Read/Write Timing
Figure 2. Video Input/Output Timing
REV. B
–3–
ADV476
ABSOLUTE MAXIMUM RATINGS
1
ORDERING GUIDE
1, 2
V
CC
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
Voltage on any Digital Pin . . . . . GND – 0.5 V to V
CC
+ 0.5 V
Ambient Operating Temperature (T
A
) . . . . . –55°C to +125°C
Storage Temperature (T
S
) . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (T
J
) . . . . . . . . . . . . . . . . . . . . +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C
Vapor Phase Soldering (1 minute) . . . . . . . . . . . . . . . +220°C
Red, Green, Blue to GND
2
. . . . . . . . . . . . . . . . . . 0 V to V
CC
NOTES
1
Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2
Analog output short circuit to any power supply or common can be of an indefinite
duration.
Model
ADV476KN35
ADV476KN50
ADV476KN66
ADV476KP35
ADV476KP50
ADV476KP66
Speed
35 MHz
50 MHz
66 MHz
35 MHz
50 MHz
66 MHz
Package Type
28-Pin DIP
28-Pin DIP
28-Pin DIP
44-Pin PLCC
44-Pin PLCC
44-Pin PLCC
Package
Option
3
N-28
N-28
N-28
P-44A
P-44A
P-44A
OBS
Parameter
PLCC
NOTES
1
All devices are specified for 0°C to +70°C operation.
2
Devices are packaged in 0.6" 28-pin plastic DIPs (N-28), and 44-pin J-leaded
PLCC (P-44A).
3
N = Plastic DIP; P = Plastic Leaded Chip Carrier.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
T
A
R
L
I
REF
Min
4.5
0
–3
Typ
5.00
Max
5.5
+70
–10
Units
Volts
°C
Ω
mA
Power Supply
Ambient Operating Temperature
Output Load
Reference Current
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADV476 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATIONS
OLE
TE
37.5
WARNING!
ESD SENSITIVE DEVICE
DIP
The above pins allow the ADV476KP (44-Pin PLCC) to be al-
ternatively driven by a voltage reference. If it is desired to use a
voltage reference configuration instead of the current reference
configuration described in this data sheet, the above listed pins
must be connected as described in Figure 6 of the ADV478/
ADV471 data sheet of this reference manual.
–4–
REV. B
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