CY7C1380DV25-200AC datasheet, PDF

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CY7C1380DV25-200AC: DescriptionCache SRAM, 512KX36, 3ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100; Categorystorage storage; File Size790KB，30 Pages; ManufacturerCypress Semiconductor

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CY7C1380DV25-200AC Overview

Cache SRAM, 512KX36, 3ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

CY7C1380DV25-200AC Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	QFP
package instruction	LQFP,
Contacts	100
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	3 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PQFP-G100
JESD-609 code	e0
length	20 mm
memory density	18874368 bit
Memory IC Type	CACHE SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	100
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512KX36
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	225
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD (800)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	14 mm
Base Number Matches	1

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PRELIMINARY

CY7C1380DV25

CY7C1382DV25

18-Mbit (512K x 36/1M x 18) Pipelined SRAM

Features

• Supports bus operation up to 250 MHz

• Available speed grades are 250, 225, 200,167, and

133 MHz

• Registered inputs and outputs for pipelined operation

• 2.5V core power supply

• Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

— 2.8 ns (for 225-MHz device)

— 3.0 ns (for 200-MHz device)

— 3.4 ns (for 167-MHz device)

— 4.2 ns (for 133-MHz device)

• Provide high-performance 3-1-1-1 access rate

•

User-selectable burst counter supporting Intel

Pentium

interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

• Single Cycle Chip Deselect

• Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA

and 165-ball fBGA packages

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• “ZZ” Sleep Mode Option

Functional Description

[1]

The CY7C1380DV25/CY7C1382DV25 SRAM integrates

524,288 x 36 and 1,048,576 x 18 SRAM cells with advanced

synchronous peripheral circuitry and a two-bit counter for

internal burst operation. All synchronous inputs are gated by

registers controlled by a positive-edge-triggered Clock Input

(CLK). The synchronous inputs include all addresses, all data

inputs, address-pipelining Chip Enable (CE

), depth-

expansion Chip Enables (CE

and CE

3[2]

), Burst Control

inputs (ADSC, ADSP, and ADV), Write Enables (BW

, and

BWE), and Global Write (GW). Asynchronous inputs include

the Output Enable (OE) and the ZZ pin.

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to two or four bytes wide as

controlled by the byte write control inputs. GW when active

LOW causes all bytes to be written.

The CY7C1380DV25/CY7C1382DV25 operates from a +2.5V

core power supply while all outputs may operate with a +2.5

supply. All inputs and outputs are JEDEC-standard JESD8-5-

compatible.

Selection Guide

250 MHz

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

2.6

350

225 MHz

2.8

325

200 MHz

3.0

300

167 MHz

3.4

275

133 MHz

4.2

245

Unit

Shaded areas contain advance information.

Please contact your local Cypress sales representative for availability of these parts.

Notes:

1. For best-practices recommendations, please refer to the Cypress application note

System Design Guidelines

on www.cypress.com.

2. CE

, CE

are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable.

Cypress Semiconductor Corporation

Document #: 38-05546 Rev. **

•

3901 North First Street

•

San Jose

CA 95134

•

408-943-2600

Revised August 12, 2004

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