UPD44322322GF-A50 datasheet, PDF

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UPD44322322GF-A50: DescriptionCache SRAM, 1MX32, 3.1ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, LQFP-100; Categorystorage storage; File Size727KB，40 Pages; ManufacturerNEC Electronics

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UPD44322322GF-A50 Overview

Cache SRAM, 1MX32, 3.1ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, LQFP-100

UPD44322322GF-A50 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	QFP
package instruction	LQFP,
Contacts	100
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	3.1 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PQFP-G100
JESD-609 code	e0
length	20 mm
memory density	33554432 bit
Memory IC Type	CACHE SRAM
memory width	32
Number of functions	1
Number of terminals	100
word count	1048576 words
character code	1000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	1MX32
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	1.7 mm
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm
Base Number Matches	1

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PRELIMINARY DATA SHEET

MOS INTEGRATED CIRCUIT

PD44322182, 44322322, 44322362

32M-BIT CMOS SYNCHRONOUS FAST SRAM

PIPELINED OPERATION

SINGLE CYCLE DESELECT

Description

The

PD44322182 is a 2,097,152-word by 18-bit,

PD44322322 is a 1,048,576-word by 32-bit and the

PD44322362 is

a 1,048,576-word by 36-bit synchronous static RAM fabricated with advanced CMOS technology using Full-CMOS six-

transistor memory cell.

The

PD44322182,

PD44322322 and

PD44322362 integrates unique synchronous peripheral circuitry, 2-bit burst

counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single clock

input (CLK).

The

PD44322182,

PD44322322 and

PD44322362 are suitable for applications which require synchronous operation,

high speed, low voltage, high density and wide bit configuration, such as buffer memory.

ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”). In

the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal operation.

The

PD44322182,

PD44322322 and

PD44322362 are packaged in 100-pin PLASTIC LQFP with a 1.4 mm package

thickness or 165-pin PLASTIC FBGA for high density and low capacitive loading.

Features

•

3.3 V or 2.5 V core supply

•

Synchronous operation

•

Operating temperature : T

= 0 to 70 °C (-A44, -A50, -A60, -C50, -C60)

= –40 to +85 °C (-A44Y, -A50Y, -A60Y, -C50Y, -C60Y)

•

Internally self-timed write control

•

Burst read / write : Interleaved burst and linear burst sequence

•

Fully registered inputs and outputs for pipelined operation

•

Single-Cycle deselect timing

•

All registers triggered off positive clock edge

•

3.3 V or 2.5 V LVTTL Compatible : All inputs and outputs

•

Fast clock access time : 2.8 ns (225 MHz), 3.1 ns (200 MHz), 3.5 ns (167 MHz)

•

Asynchronous output enable : /G

•

Burst sequence selectable : MODE

•

Sleep mode : ZZ (ZZ = Open or Low : Normal operation)

•

Separate byte write enable : /BW1 to /BW4, /BWE (

PD44322322,

PD44322362)

/BW1, /BW2, /BWE (

PD44322182)

Global write enable : /GW

•

Three chip enables for easy depth expansion

•

Common I/O using three state outputs

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all products and/or types are available in every country. Please check with NEC Electronics sales

representative for availability and additional information.

Document No. M16355EJ1V0DS00 (1st edition)

Date Published December 2002 NS CP(K)

Printed in Japan

The mark

shows major revised points.

2002

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