DS21Q50N datasheet, PDF - EEWORLD Datasheet

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DS21Q50N: DescriptionTelecom IC,; CategoryWireless rf/communication Telecom circuit; File Size325KB，99 Pages; ManufacturerDALLAS; Websitehttp://www.dalsemi.com

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Telecom IC,

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DS21Q50

Quad E1 Transceiver

www.dalsemi.com

PRELIMINARY

FEATURES

4 complete E1 (CEPT) PCM-30/ISDN-PRI

transceivers

Long and short haul line interfaces

32-bit or 128-bit crystal-less jitter attenuator

Frames to FAS, CAS, CCS, and CRC4 formats

4/8/16MHz clock synthesizer

Flexible system clock with automatic source

switching on loss of clock source

Two–frame elastic store slip buffer on the receive

side

Interleaving PCM bus operation up to 16.384MHz

Configurable parallel and serial port operation

Detects and generates remote and AIS alarms

Fully independent transmit and receive functionality

Four separate loopback functions

PRBS generation/detection/error counting

3.3V low power CMOS

100-PIN

LQFP

100

ORDERING INFORMATION

DS21Q50L:

100-pin 14mm LQFP (0

C to 70

DS21Q50LN:

100-pin 14mm LQFP (-40

C to 85

Large counters for bipolar and code

violations, CRC4 code word errors, FAS

word errors, and E bits

8 additional user configurable output pins.

100-pin LQFP package (14mm)

DESCRIPTION

The DS21Q50 E1 Quad Transceiver contains all of the necessary functions for connection to 4 E1 lines. The

onboard clock/data recovery circuitry coverts the AMI/HDB3 E1 waveforms to an NRZ serial stream. The

DS21Q50 automatically adjusts to E1 22AWG (0.6 mm) twisted–pair cables from 0 to over 2km in length. The

device can generate the necessary G.703 waveshapes for both 75 ohm coax and 120 ohm twisted pair cables.

The onboard jitter attenuators (selectable to either 32 bits or 128 bits) can be placed in either the transmit or

receive data paths. The framers locate the frame and multiframe boundaries and monitor the data streams for

alarms. The device contains a set of internal registers, which the user can access and control the operation of the

unit via the parallel control port or serial port. The device fully meets all of the latest E1 specifications including

ITU-T G.703, G.704, G.706, G.823, G.732, and I.431, ETS 300 011, 300 233, and 300 166, as well as

CTR12 and CTR4.

Page 1 of 99

051401

DS21Q50

TABLE OF CONTENTS

FEATURES.........................................................................................................................1

ORDERING INFORMATION .........................................................................................1

DESCRIPTION ..................................................................................................................1

1. LIST OF FIGURES .....................................................................................................4

2. LIST OF TABLES .......................................................................................................5

3. INTRODUCTION .......................................................................................................6

4. FUNCTIONAL DESCRIPTION ................................................................................6

4.1

DOCUMENT REVISION HISTORY.....................................................................7

5. PIN DESCRIPTION....................................................................................................9

5.1 PIN FUNCTION DESCRIPTION........................................................................15

5.1.1 System (Backplane) Interface Pins ................................................................15

5.1.2 Alternate Jitter Attenuator ............................................................................16

5.1.3 Clock Synthesizer...........................................................................................16

5.1.4 Parallel Port Control Pins.............................................................................17

5.1.5 Serial Port Control Pins ................................................................................18

5.1.6 Line Interface Pins.........................................................................................19

5.1.7 Supply Pins.....................................................................................................20

6. HOST INTERFACE PORT ......................................................................................21

6.1

6.2

6.3

ARALLEL

ORT

PERATION

.................................................................................21

ERIAL

ORT

PERATION

......................................................................................21

7. CONTROL, ID, AND TEST REGISTERS .............................................................25

7.1

7.2

7.3

7.4

7.5

OWER

–U

EQUENCE

...........................................................................................26

RAMER

OOPBACK

...............................................................................................29

UTOMATIC

LARM

ENERATION

........................................................................31

EMOTE

OOPBACK

...............................................................................................32

OCAL

OOPBACK

.................................................................................................32

8. STATUS AND INFORMATION REGISTERS......................................................35

8.1

CRC4 S

YNC

OUNTER

...........................................................................................37

9. ERROR COUNT REGISTERS................................................................................43

9.1

9.2

9.3

9.4

BPV

ODE

IOLATION

OUNTER

.....................................................................43

CRC4 E

RROR

OUNTER

.........................................................................................44

E–B

/ PRBS B

RROR

OUNTER

......................................................................45

FAS E

RROR

OUNTER

...........................................................................................46

Page 2 of 99

DS21Q50

1. LIST OF FIGURES

Figure 1-1 DS21Q50 QUAD TRANSCEIVER............................................................................................. 8

Figure 3-1 SERIAL PORT OPERATION MODE 1 ................................................................................... 21

Figure 3-2 SERIAL PORT OPERATION MODE 2 ................................................................................... 22

Figure 3-3 SERIAL PORT OPERATION MODE 3 ................................................................................... 23

Figure 3-4 SERIAL PORT OPERATION MODE 4 ................................................................................... 23

Figure 16-1 EXTERNAL ANALOG CONNECTIONS (BASIC CONFIGURATION)............................. 69

Figure 16-2 EXTERNAL ANALOG CONNECTIONS (PROTECTED INTERFACE) ............................. 70

Figure 16-3 TRANSMIT WAVEFORM TEMPLATE ............................................................................... 71

Figure 16-4 JITTER TOLERANCE ............................................................................................................ 73

Figure 16-5 JITTER ATTENUATION........................................................................................................ 73

Figure 17-1 CMI CODING ........................................................................................................................ 75

Figure 17-2 EXAMPLE OF CMI CODE VIOLATION (CV) .................................................................... 75

Figure 18-1 IBO CONFIGURATION USING 2 DS21Q50 TRANSCEIVERS (8 E1 Lines)...................... 78

Figure 19-1 RECEIVE FRAME AND MULTIFRAME TIMING ............................................................... 79

Figure 19-2 RECEIVE BOUNDARY TIMING (with elastic store disabled) ................................................ 79

Figure 19-3 RECEIVE BOUNDARY TIMING (with elastic store enabled)................................................. 79

Figure 19-4 RECEIVE INTERLEAVE BUS OPERATION ........................................................................ 80

Figure 19-5 TRANSMIT FRAME AND MULTIFRAME TIMING............................................................ 81

Figure 19-6 TRANSMIT BOUNDARY TIMING....................................................................................... 81

Figure 19-7 TRANSMIT INTERLEAVE BUS OPERATION .................................................................... 82

Figure 19-8 DS21Q50 FRAMER SYNCHRONIZATION FLOWCHART................................................ 83

Figure 19-9 DS21Q50 TRANSMIT DATA FLOW.................................................................................... 84

Figure 21-1 INTEL BUS READ AC TIMING (BTS=0 / MUX = 1) ........................................................... 87

Figure 21-2 INTEL BUS WRITE TIMING (BTS=0 / MUX=1).................................................................. 87

Figure 21-3 MOTOROLA BUS AC TIMING (BTS = 1 / MUX = 1) ......................................................... 88

Figure 21-4 INTEL BUS READ TIMING (BTS=0 / MUX=0).................................................................... 90

Figure 21-5 INTEL BUS WRITE TIMING (BTS=0 / MUX=0).................................................................. 90

Figure 21-6 MOTOROLA BUS READ TIMING (BTS=1 / MUX=0) ........................................................ 91

Figure 21-7 MOTOROLA BUS WRITE TIMING (BTS=1 / MUX=0)....................................................... 91

Figure 21-8 SERIAL BUS TIMING (BIS1 = 1, BIS0 = 0).......................................................................... 92

Figure 21-9 RECEIVE AC TIMING (Receive elastic store disabled) ........................................................... 94

Figure 21-10 RECEIVE AC TIMING (Receive elastic store enabled).......................................................... 95

Figure 21-11 TRANSMIT AC TIMING (IBO Disabled)............................................................................. 97

Figure 21-12 TRANSMIT AC TIMING (IBO Enabled).............................................................................. 97

Figure 21-13 NRZ INPUT AC TIMING..................................................................................................... 98

Page 4 of 99

DS21Q50

2. LIST OF TABLES

Table 5-1 PIN TABLE (By Function) ............................................................................................................ 9

Table 5-2 PIN TABLE (By LQFP Pin Number).......................................................................................... 12

Table 5-3 CSBGA Ball Assignment ............................................................................................................. 15

Table 6-1 BUS MODE SELECT ................................................................................................................ 21

Table 6-2 REGISTER MAP SORTED BY ADDRESS............................................................................... 24

Table 7-1 SYNC/RESYNC CRITERIA...................................................................................................... 27

Table 8-1 ALARM CRITERIA................................................................................................................... 38

Table 11-1 TRANSMIT PRBS MODE SELECT........................................................................................ 51

Table 11-2 RECEIVE PRBS MODE SELECT ........................................................................................... 52

Table 12-1 MASTER PORT SELECTION................................................................................................. 54

Table 12-2 SYNTHESIZER OUTPUT SELECT ........................................................................................ 54

Table 18-1 OUTA AND OUTB FUNCTION SELECT ............................................................................. 64

Table 19-1 LINE BUILD OUT SELECT IN LICR..................................................................................... 68

Table 19-2 TRANSFORMER SPECIFICATIONS .................................................................................... 69

Table 21-1 IBO DEVICE ASSIGNMENT ................................................................................................. 77

Table 21-2 IBO SYSTEM CLOCK SELECT............................................................................................. 77

Page 5 of 99

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