Preliminary Specifications
CMOS LSI
LE25FW106M
LE25FW106T
1M-bit (128K x 8) Serial Flash Memory
■
Outline
LE25FW106 is 128K x 8-bit Serial flash memory by 3.0V single power supply operation, and support serial peripheral
interface (S.P.I.). There are three kinds of erase functions, Chip erase, Sector (32 K bytes) erase and small sector (2K
bytes) erase. Moreover, Page program can program the arbitrary data to 1 byte from 256 bytes. Program time is
30us/byte(Typ.), 1.5ms(Typ.) / 256bytes, and high speed. It is best suited for application that requires
re-programmable nonvolatile mass storage of program or data memory.
■
Feature
Read / Write Operation by the 3.0V single power supply are possible: Power Supply Voltage Range 2.7-3.6V
Clock frequency:
Temperature range:
Sector size:
2 K bytes / small sector
32 K bytes / sector
Small sector erase, Sector erase, Chip erase function
Page program (256 bytes/page)
Block protection
A high reliability Read / Write
Endurance cycles:
Small sector erase time:
Sector erase time:
Chip erase time:
Page program time:
Status function:
Data retention: 10 years
Package available:
LE25FW106M
LE25FW106T
SOP8
MSOP8
100,000 times
25ms (Typ.)
0.5s (Max.)
25ms (Typ.)
0.5s (Max.)
100ms (Typ.)
5s (Max.)
30 us/byte (Typ.) 1.5ms/256 bytes (Typ.) 2.5 ms/256 bytes (Max.)
30 MHz
0 ~ +70 °C / -45 ~ +85 °C (Planning)
Serial interface: SPI Mode0 and Mode3 correspondence
Ready / busy information, Erase time excess information, Protection information
Figure 1: Pin Assignment
*This product incorporate technology licensed from Silicon Storage Technology, Inc.
This
preliminary
specification is subjected to change without notice.
SANYO Electric Co., Ltd. Semiconductor Company
1-1, 1 Chome, Sakata, Oizumi-machi, Ora-gun, GUNMA, 370-0596 JAPAN
Revision 2.1 – May. 11, 2004
1/17
LE25FW106M / LE25FW106T
3.0V only 1 M-bit Serial Flash Memory
Preliminary Specifications
Figure 2: Block diagram
ADDRESS
BUFFERS
&
LATCHES
X-
DECODER
1M bit
Flash EEPROM
Cell Array
Y-DECODER
CONTROL
LOGIC
I/O BUFFERS
&
DATA LATCHES
SERIAL INTERFACE
CS#
SCK
SI
SO
WP#
HOLD#
Table 1: Pin Description
Symbol
SCK
SI
SO
CS#
Pin Description
Serial clock
Serial data input
Serial data output
Chip select
Function
To control the timing of serial data input and output.
To latch input data and addresses synchronously at the rising edge of SCK, and read out
Output data synchronously at the falling edge.
To input data or addresses serially from MSB to LSB (Least Significant Bit).
To output data serially from MSB to LSB.
To activate the device when this pin is LOW.
To deselect and put the device to standby mode when this pin is HIGH.
To write-protect the Block Protect bits (BP0, BP1) and the Status Register Write Protect bit
WP#
HOLD#
VDD
VSS
Write-protect
Hold
Power supply
Ground
(SRWP) of the Status Register in co-operation with the Status Register Write Protect bit
(SRWP).
To pause any serial communications with the device without deselecting the device.
To provide from 2.7V to 3.6V supply
SANYO Electric Co., Ltd.
No. 2
LE25FW106M / LE25FW106T
3.0V only 1 M-bit Serial Flash Memory
Preliminary Specifications
Table 2: Commands Summary
Command
The 1st bus
cycle
(OP-code)
03h
Read
0Bh
Small sector erase
Sector erase
Chip erase
Page program
Write Enable
Write disable
Power down
Status register Read
Status register Write
Software reset
Read ID
ABh
Release from power down
Definition of Table 2:
X = don't care, h = hexadecimal notation, A23-A17 are don't care for all commands
*1. A10-A8 are don't care
*2. A14-A8 are don't care
*3. PD: page program data. The arbitrary numbers of data of 1 byte - 256 bytes of byte unit for input.
*4. Read ID A7-A1 are don't care. A read cycle from address A0=‘0’ outputs the manufacture code (SANYO: 62h). A read cycle at address
A0=‘1’ outputs the device code (15h).
X
X
A7-A0 *4
D7h
D8h
C7h
02h
06h
04h
B9h
05h
01h
FFh
DATA
A23-A16
A15-A8
A7-A0
PD *3
PD *3
PD *3
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8 *1
A15-A8 *2
A7-A0
X
X
X
The 2nd bus
cycle
A23-A16
The 3rd bus
cycle
A15-A8
The 4th bus
cycle
A7-A0
The 5th bus
cycle
The 6th bus
cycle
The n-th bus
cycle
Table 3: Status register
Bit
Bit0
Name
RDY#
Logic
0
1
0
1
0
1
0
1
Reserve bit
ERSER
0
1
Erase normal operation / normal end
Erase time excess state
Reserve bit
SRWP
0
1
Status register
Status register
Write enable state
Write disable state
The block protect information
Reference status registers
Function
Ready state
A program / erase state
Write prohibition state
Write possible state
Default at Power up
0
Bit1
WEN
0
Non-volatile
information
Non-volatile
Information
0
0
0
Non-volatile
Information
Bit2
BP0
Bit3
Bit4
Bit5
Bit6
Bit7
BP1
SANYO Electric Co., Ltd.
No. 3
LE25FW106M / LE25FW106T
3.0V only 1 M-bit Serial Flash Memory
Preliminary Specifications
Device operation
LE25FW106 is the product that supports the serial interface,
and has the electric on-chip erase by the 3.0V single power
supply and the function of standard EPROM for industrial. The
interface and control are made easily by building a command
register in a chip. Reading, erasing, programming, and a function
required in addition to them are performed through a command
register.
The address and data of command are latched for program and
erase operation.
Figure3 and figure4 indicate the timing waveform of serial input
and output.
While CS# is LOW, the device will be chosen and the input of a
command, an address, etc. can be attained serially. Those inputs
are performed from Bit7 (MSB) synchronizing with the rising edge
of SCK. At this time, an output terminal (SO) is in a high
impedance state.
It is that an output terminal (SO) will be in a low impedance state
at the time of a Read, a status register Read, and Silicone ID, and
data is outputted from Bit7 (MSB) synchronizing with falling edge
of a clock.
LE25FW106 support the both sides of serial interface SPI
mode0 and SPI mode3. In case CS# falling edge, if SCK is in a
logic low level state and it is in SPI mode0, and if a high level
state, SPI mode3 will be chosen automatically.
2. Status Register
The status register's contents are shown in Table3.
The status register can perform detection state of a device and
setup of protection.
2-1. Status register read
The status register's contents can be read by status register
read, moreover it can read also during the following operation.
•
Small sectors erase
•
Sectors erase
•
Chips erase
•
Page program
•
Status register Write
Figure6 shows timing waveform of a status register Read.
Status register command consists of only the 1st bus, If
OP-code (05h) dose writes in, synchronizing with falling edge of
SCK, the status register's contents will be outputted from SRWP
(Bit7).
If the data is outputted until RDY# (Bit0), and also SCK input
continues still more, it returns to SRWP and data output is
continued. Data is outputted from the falling edge clock of the 1st
bus cycle Bit0.
Status register Read can be read always (also in case of inside
of program cycle or erase cycle).
2-2. Status register Write
By Status register Write, BP0 and BP1, and SRWP can be
rewritten. BSY#, WEN, ERSER, and Bit4 and Bit6 are read-only,
and BP0, BP1, and SRWP are non-volatile.
A timing waveform is shown in Figure7 and a flow chart is
shown in Figure17.
Status register Write command consists of the 1st bus cycle
and the 2nd bus cycle, and internal Write operation starts with the
rising edge of CS# after inputting data after OP-code (01h). Erase
and program are automatically performed inside the device and a
Status register Write rewrites BP0, BP1, and SRWP
non-volatilized data. The write-in data to read-only bits (RDY#,
WEN, ERSER, Bit 4 and Bit 6) are don't care.
The end of a status register Write is detectable with RDY# of a
status register Read.
The number of times of rewriting of a status register Write is
10,000 times (Min).
In order to perform a status register Write, it is necessary to
change WEN of a status register into "1" state for WP# pin.
RDY#(Bit0)
The end of a Write (program, erase, status register Write) is
detectable with RDY#. If device is in a busy state RDY# is in "1",
and the Write will be ended in "0" states.
Command definition
Table2 contains a command list and a brief summary of the
commands. The following is a detailed description of the options
initiated by each command.
1. Read
Figure5 shows timing waveform of a Read operation.
There are two kinds of Read commands, 4th bus Read and 5th
bus Read. The 4th bus read is constituted from the 1st bus cycle
to the 4th bus cycle. If 24-bit address is inputted after OP-code
(03h), the data of the specified address will be outputted
synchronizing with SCK. A data is outputted from the falling edge
clock of the 4th bus cycle Bit0.
5th bus Read is constituted from the 1st bus cycle by the 5th
bus cycle, which consists of 24 bits address and 8-bit dummy bit
after OP-code (0Bh). The data is outputted from the falling edge
clock of the 5th bus cycle Bit0. The only one difference between
these two commands is with or without a dummy bit input (5th bus
cycle).
While having inputted SCK, the increment of the address is
automatically carried out inside a device, and data is outputted in
order until the top address (1FFFFh) up to. If the data is outputted
and the input of SCK continues still more, it returns to the lowest
address (00000h) and a data output is continued.
By making CS# into a logic high level, a device is deselecting,
and read cycle is ended. Output terminal will be in a high
impedance state.
SANYO Electric Co., Ltd.
No. 4
LE25FW106M / LE25FW106T
3.0V only 1 M-bit Serial Flash Memory
Preliminary Specifications
WEN (Bit1)
It is detectable whether a Write is possible with WEN. If WEN is
in "0" state, even if it inputs a Write command, Device will not
perform write operation. If WEN is in "1" state, Write is possible to
the area by which block protection is not carried out.
WEN is controllable with a Write Enable command and a Write
disable command. WEN will be in "1" state with a Write Enable
command (06h), and will be in "0" states with a Write disable
command (04h).
Moreover, in the following state, automatically, WEN will be in
"0" states and an unprepared Write will be prevented.
•
At the time of a power-up
•
After small sector erase, sector erase, or chip erase is
completed
•
After a page program is completed
•
After a status register Write is completed
BP0 and BP1 (Bit 2 and 3)
Block protection BP0 and BP1 can set up the memory address
area to be protected. Refer to Table 4 for setting conditions.
Table 5: SRWP setting conditions
WP# pin
SRWP
0
1
1
0
1
Bit4 and Bit6 are reserve bit.
Status register
protection state
Unprotect
Protection
Unprotect
Unprotect
0
3. Write Enable
Write Enable sets a status register WEN to "1" state. In order to
perform the following operation, it is necessary to execute a Write
Enable command first.
•
Small sector erase
•
Sector erase
•
Chip erase
•
Page program
•
Status register Write
Figure8 shows timing waveform. A Write Enable command
consists of only the 1st bus cycle. OP-code is 06h.
Table 4: Protection level setting conditions
Protection level
Status register
bit
BP1
BP0
Protection area
0
0
0
Nothing
(all area unprotect)
1
0
1
18000h - 1FFFFh
(1/4 protection)
2
1
0
10000h - 1FFFFh
(1/2 protection)
3
1
1
00000h - 1FFFFh
(all area protection)
* A chip erase is possible only when a protection level is 0.
ERSER (Bit5)
Erase time excess flag ESRER will be in "1" state, if an erase
exceeds regulation marginal time. The regulation marginal time of
small sector erase and sector erase is 2s (Typ.), and in case of
chip erase, it is 10s (Typ.). If an erase exceeds regulation
marginal time, a device will be locked and an erase will not end it
automatically (it continues being in a busy state). In order to make
it end, it is necessary to perform software reset.
SRWP (Bit7)
Status register Write protection SRWP protects status register.
When "1" state and WP# pin are logic low levels, as for a status
register Write command, they are disregarded, and as for BP0
and BP1 of a status register, and SRWP is protected. When WP#
pin is a logic high level, a status register is not protected
irrespective of the state of SRWP. SRWP setting conditions are
shown in Table 5.
4. Write disable
Write disable sets a status register WEN to "0" states, and
forbids an unprepared Write.
Figure9 shows timing waveform. Write Enable command
consists of only the 1st bus cycle. OP-code is 04h.
To release from a Write disable state (WEN "0"), it should be
performed the Write Enable command (06h).
5. Power Down
Power down states carry out the prohibition state of all the
commands except Read ID and power down release command.
Figure10 shows timing waveform. Power down command
consists of only the 1st bus cycle. OP-code is B9h.
For release from power down mode, Power down release
command performs to abort.
Figure11 shows release from power down timing waveform.
And figure16 shows Read ID timing waveform.
6. Small Sector Erase
Small sector erase function is changes the memory cell data of
arbitrary small sectors into "1" state. Small sector consists of 2 K
bytes.
Figure12 shows timing waveform and a flow chart is shown in
Figure18.
Small sector erase command is constituted from the 1st bus
cycle to the 4th bus cycle, 24-bit address after OP-code (D7h). As
for the address, A16-A11 are effective, and the rest is don't care.
Erase operation begins from the rising edge of CS# after a
command input end, and it ends automatically by control of an
internal timer. Moreover, the end of an erase is detectable by
using status register.
However, when it becomes an excess of an erase time (a
status register ESRER is "1" state), small sector erase mode is
not ended automatically. In order to make it end, it is necessary to
perform software reset input.
SANYO Electric Co., Ltd.
No. 5
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