Agilent HFCT-5103B/D SC Duplex
Single Mode Transceiver
Data Sheet
Features
• SC duplex single mode
transceiver
• Single +5 V power supply
• Multisourced 1 x 9 pin
configuration
• Aqueous washable plastic
package
• Interchangeable with
HFBR-5103 and other LED
multisourced 1 x 9 transceivers
• Unconditionally eye safe laser IEC
825/CDRH Class 1 compliant
• Conforms to ANSI X3.184-1993
standard for FDDI SMF-PMD
Category 1 Optoelectronic
performance
• Compatible with the HFCT-5205
Applications
• FDDI SMF-PMDl
• Fast ethernet
• ATM compatible
Description
The HFCT-5103 transceiver is a
high performance, cost effective
module for serial optical data
communications applications
specified for a signal rate of
125 MBd. It is designed to provide
an FDDI SMF-PMDl link for FDDI
or Fast Ethernet applications and
is also compatible with
ATM/SONET/SDH transceivers.
This module is designed for single
mode fiber and operates at a
nominal wavelength of 1300 nm.
It incorporates Agilent’s high
performance, reliable, long
wavelength optical devices and
proven circuit technology to give
long life and consistent service.
The transmitter section uses a
Multiple Quantum Well laser with
full IEC 825 and CDRH Class I eye
safety.
The receiver section uses an
MOVPE grown planar PIN
photodetector for low dark
current and excellent
responsivity.
A pseudo-ECL logic interface
simplifies interface to external
circuitry.
Connection Diagram
RECEIVER SIGNAL GROUND
o
1
RECEIVER DATA OUT
o
2
RECEIVER DATA OUT BAR
o
3
SIGNAL DETECT
o
4
RECEIVER POWER SUPPLY
o
5
TRANSMITTER POWER SUPPLY
o
6
TRANSMITTER DATA IN BAR
o
7
TRANSMITTER DATA IN
o
8
TRANSMITTER SIGNAL GROUND
o
9
N/C
Top View
N/C
Pin Descriptions:
Pin 1 Receiver Signal Ground V
EER
:
Directly connect this pin to the
receiver ground plane.
Pin 2 Receiver Data Out RD:
See recommended circuit
schematic, Figure 4.
Pin 3 Receiver Data Out Bar RD:
See recommended circuit
schematic, Figure 4.
Pin 4 Signal Detect SD:
Normal optical input levels to the
receiver result in a logic “1”
output.
Low optical input levels to the
receiver result in a fault condition
indicated by a logic “0” output.
This Signal Detect output can be
used to drive a PECL input on an
upstream circuit, such as Signal
Detect input or Loss of Signal-bar.
Pin 5 Receiver Power Supply V
CCR
:
Provide +5 V dc via the
recommended transmitter power
supply filter circuit. Locate the
power supply filter circuit as close
as possible to the V
CC
pin.
Pin 6 Transmitter Power Supply V
CCT
:
Provide +5 V dc via the
recommended transmitter power
supply filter circuit. Locate the
power supply filter circuit as close
as possible to the V
CC
pin.
Pin 7 Transmitter Data In Bar TD:
See recommended circuit
schematic, Figure 4.
Pin 8 Transmitter Data In TD:
See recommended circuit
schematic, Figure 4.
Pin 9 Transmitter Signal Ground V
EET
:
Directly connect this pin to the
transmitter ground plane.
Mounting Studs
The mounting studs are provided
for mechanical attachment to the
circuit board. They are embedded
in the nonconductive plastic
housing and are not tied to the
transceiver internal circuit and
should be soldered into
plated-through holes on the
printed circuit board.
2
Functional Description
Receiver Section
Design
The receiver section contains an
InGaAs/InP photo detector and a
preamplifier within the receptacle,
coupled to a postamp/decision
circuit on a separate circuit board.
The postamplifier is ac coupled to
the preamplifier as illustrated in
Figure 1. The coupling capacitor
is large enough to pass the FDDI
test pattern at 125 MBd and the
SONET/SDH test pattern at
155 MBd without significant
distortion or performance penalty
If a lower signal rate, or a code
which has significantly more low
frequency content is used,
sensitivity, jitter and pulse
distortion could be degraded.
Figure 1 also shows a filter
network which limits the
bandwidth of the preamp output
signal. The filter is designed to
bandlimit the preamp output
noise and thus improve the
receiver sensitivity.
These components will also
reduce the sensitivity of the
receiver as the signal bit rate is
increased above 155 MBd.
Noise Immunity
The receiver includes internal
circuit components to filter
power supply noise. Under some
EMI and power supply noise
conditions, external power supply
filtering may be necessary. If
receiver sensitivity is degraded by
power supply noise, the filter
network illustrated in Figure 2
may be employed to improve
performance. The values of the
filter components are general
recommendations and may be
changed to suit a particular
system environment. Shielded
inductors are recommended.
Terminating the Outputs
The PECL Data outputs of the
receiver may be terminated with
the standard Thevenin-equivalent
50 ohm to V
CC
-2 V termination.
Other standard PECL terminating
techniques may be used.
The two outputs of the receiver
should be terminated with
identical load circuits to avoid
unnecessary large ac current in
V
CC
. If the outputs are loaded
identically, the ac current is
largely nulled. The Signal Detect
output of the receiver is PECL
logic and must be loaded if it is to
be used. The Signal Detect circuit
is much slower that the data path,
so the ac noise generated by an
asymmetrical load is negligible.
Power consumption may be
reduced by using a higher than
normal load impedance for the
Signal Detect output.
Transmission line effects are not
generally a problem as the
switching rate is slow.
The Signal Detect Circuit
The Signal Detect circuit works
by sensing the peak level of the
received signal and comparing
this level to a reference.
TRANS-
IMPEDANCE
PRE-
AMPLIFIER
RECEIVER
RECEPTACLE
FILTER
LIMITING
AMPLIFIER
DATA OUT
PECL
OUTPUT
BUFFER
DATA OUT
GND
SIGNAL
DETECT
CIRCUIT
PECL
OUTPUT
BUFFER
SD
Figure 1 - Receiver Block Diagram
3.3 µH
V
CC
100 nF
100 nF
FILTERED V
CC
to DATA LINK
+
10 µF
Figure 2 -
p
Filter Network for Noise Filtering
3
Functional Description
Transmitter Section
Design
The transmitter section, Figure 3,
uses a Multiple Quantum Well
laser as its optical source. The
packaging of this laser is designed
for repeatable coupling into single
mode fiber while maintaining
compliancy with IEC 825 Class 1
and CDRH Class I eye safety
requirements. The optical output
is controlled by a custom IC which
detects the laser output via the
monitor photodiode. This IC
provides both dc and ac current
drive to the laser to ensure correct
modulation, eye diagram and
extinction ratio over temperature,
supply voltage and life.
PCB mounting
The HFCT-5103 has two
solderable mounting studs. These
studs are not electrically
connected. The transceiver is
designed for common production
processes. It may be wave
soldered and aqueous washed
providing the process plug is in
place.
Each process plug can only be
used once during processing,
although with subsequent use, it
can be used as a dust cover.
LASER
PHOTODIODE
(rear facet monitor)
DATA
DATA
PECL
INPUT
LASER
MODULATOR
LASER BIAS
DRIVER
LASER BIAS
CONTROL
Figure 3 - Simplified Transmitter Schematic
4
NO INTERNAL
CONNECTION
TOP VIEW
NO INTERNAL
CONNECTION
V
EER
1
RD
2
RD
3
SD
4
V
CCR
5
V
CCT
6
TD
7
TD
8
V
EET
9
C1 C7
L1
C3
R7
C6
R8
R10
R9
C8 C2
V
CC
L2
C4
R1
C5
R4
R2
R3
NOTES:
THE SPLIT-LOAD TERMINATIONS FOR ECL SIGNALS
NEED TO BE LOCATED AT THE INPUT OF DEVICES
RECEIVING THOSE ECL SIGNALS. RECOMMEND
4-LAYER PRINTED CIRCUIT BOARD WITH 50
MICROSTRIP SIGNAL PATHS BE USED.
R1 = R4 = R6 = R8 = R10 = 130
R2 = R3 = R5 = R7 = R9 = 82
C1 = C2 = 10 µF (see Figure 2)
C3 = C4 = C7 = C8 = 100 nF
C5 = C6 = 0.1 µF
L1 = L2 = 3.3 µH COIL OR FERRITE INDUCTOR.
V
CC
TERMINATE
AT THE
DEVICE
INPUTS
R6
R5
V
cc
FILTER
AT V
cc
PINS
TRANSCEIVER
W
TERMINATION
AT
TRANSCEIVER
INPUTS
TD
TD
W
W
RD
RD
SD
V
CC
Figure 4 - Recommended Circuit Schematic
Regulatory Compliance
Feature
Electrostatic Discharge
(ESD) to the Electrical
Pins
Electrostatic Discharge
(ESD) to the Duplex SC
Receptacle
Electromagnetic
Interference (EMI)
Test Method
MIL-STD-883C
Method 3015.4
Variation of IEC 801-2
Performance
Class 1 (>1 kV) - Human Body Model
Immunity
FCC Class B
CENELEC EN55022 Class B
(CISPR 22A)
VCCI Class 1
Variation of IEC 801-3
Eye Safety
FDA CDRH 21-CFR 1040
Class I
IEC 825 Issue 1 1993:11
Class 1
CENELEC EN60825 Class 1
Products of this type, typically, withstand at least 25 kV
without damage when the Duplex SC Connector
Receptacle is contacted by a Human Body Model probe.
Typically provide a 17 dB margin to the noted standard
limits up to 6 GHz, when tested in a GTEM cell with the
transceiver mounted to a circuit card with a chassis
enclosure.
Typically show no measurable effect from a 10 V/m field
swept from 27 MHz to 1 GHz applied to the transceiver
without a chassis enclosure.
CDRH Accession Number: 9521220-27
TUV Bauart License: 933/510018/02
5
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