NM93C46ATLVMT8 datasheet, PDF - EEWORLD Datasheet

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NM93C46ATLVMT8: DescriptionEEPROM, 64X16, Serial, CMOS, PDSO8, PLASTIC, TSSOP-8; Categorystorage storage; File Size56KB，11 Pages; ManufacturerFairchild; Websitehttp://www.fairchildsemi.com/

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NM93C46ATLVMT8 Overview

EEPROM, 64X16, Serial, CMOS, PDSO8, PLASTIC, TSSOP-8

NM93C46ATLVMT8 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	SOIC
package instruction	TSSOP, TSSOP8,.25
Contacts	8
Reach Compliance Code	unknown
ECCN code	EAR99
Other features	40 YEAR DATA RETENTION
Spare memory width	8
Maximum clock frequency (fCLK)	0.25 MHz
Data retention time - minimum	40
Durability	1000000 Write/Erase Cycles
JESD-30 code	R-PDSO-G8
JESD-609 code	e0
length	4.4 mm
memory density	1024 bit
Memory IC Type	EEPROM
memory width	16
Number of functions	1
Number of terminals	8
word count	64 words
character code	64
Operating mode	SYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
organize	64X16
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP8,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Parallel/Serial	SERIAL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3/5 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Serial bus type	MICROWIRE
Maximum standby current	0.00001 A
Maximum slew rate	0.001 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	3 mm
Maximum write cycle time (tWC)	15 ms
write protect	SOFTWARE
Base Number Matches	1

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AN-758

Using Fairchild’s

MICROWIRE™ EEPROM

Fairchild Semiconductor manufactures a wide range of low den-

sity serial EEPROMs that use the MICROWIRE interface as a

means of communication. Although all of these devices use the

MICROWIRE interface, there are slight variations in interfacing

due to differences in memory sizes, features, and technology

used to implement the device. Additionally, the MICROWIRE

interface does not specifically define any protocol, it only defines

a basic set of signal lines to interconnect two or more devices. Due

to these reasons, additional information is necessary to fully

understand how to best interface to Fairchild’s family of

MICROWIRE EEPROM.

The goal of this application guide is to cover a diversity of

information in regard to basic timing, interfacing options, and

functionality of different EEPROMs. I will use an outline approach,

so the appropriate heading can be located easily. Each section

attempts to be stand alone so the information can be easily

extracted. The outline appears below:

Fairchild

Application Note 758

1.0 Description of EEPROM Families

1.1 CMOS EEPROM

Fairchild builds a range of MICROWIRE CMOS EEPROMs in

memory sizes ranging from 256-bit to 16,384-bit. The NM93C

family is the base family and the NM93CS is a similar family with

additional features, there are also other devices with slight varia-

tions on the interface. All these devices are available with certain

“standard” options such as operating temperature ranges and

operating voltage ranges, packaging options and test options.

These options being fairly standard variations for semiconductor

devices, will not be addressed beyond this. The purpose of this

article is to address basic functionality and interfacing, including

various tricks to simplify or modify the interface.

1.2 NM93C Family

The NM93C family of EEPROM is available in 256-, 1024-, 2048-,

4096-bit, and 16,384-bit sizes. All of these are internally organized in

16-bit words, therefore all data transactions deal with 16 bits. This

family of EEPROMs has 7 instructions that deal with read, write, and

a basic level of data protection. The instructions are listed in Table 1.

It is important to note that there is a basic difference in length of the

instruction between the NM93C06 or NM93C46 and the NM93C56

or NM93C66. This is due to the larger devices needing additional

address bits.

The NM93C family of EEPROM, like all of Fairchild’s serial

EEPROMs have a basic level of write protection that can be turned

on or off by the use of the ERASE/WRITE DISABLE (EWDS) and

ERASE/WRITE ENABLE (EWEN) instructions. Although there

are two erase instructions included in the NM93C family, these are

included only for compatibility with older EEPROMs that require

erase before write. These EEPROMs don’t require erase before

write and it is recommended that in application the erase not be

used as this adversely affects endurance.

OUTLINE

1. 1.0 Description of EEPROM Families

A. 1.1 CMOS EEPROM

B. 1.2 NM93C Family

C. 1.3 NM93CS Family

D. 1.4 NM93CxxA Family

2. 2.0 HARDWARE CONNECTIONS

A. 2.1. INTERFACE PIN DESCRIPTIONS

a. 2.1.1 Chip Select (CS)

b. 2.1.2 Serial Clock (SK)

c. 2.1.3 Data-In (DI)

d. 2.1.4 Data-Out (DO)

e. 2.1.5 Program Enable (PE)

f. 2.1.6 Protect Register Enable (PRE)

g. 2.1.7 Organization (ORG)

h. 2.1.8 Status (RDY/BUSY)

B. 2.2. FOUR WIRE BUS

C. 2.3. THREE WIRE BUS

3. 3.0 TIMING CONSIDERATIONS

A. 3.1 BUS TIMING

B. 3.2 INSTRUCTION SEQUENCE DESCRIPTIONS

a. 3.2.1 Read Cycle

b. 3.2.2 Sequential Read

c. 3.2.3 Erase and Erase All

d. 3.2.4 Write and Write All

e. 3.2.5 Program Enable and Program Disable

f. 3.2.6 Protect Register Read

g. 3.2.7 Protect Register Enable

h. 3.2.8 Protect Register Disable

i. 3.2.9 Protect Register Clear

j. 3.2.10 Protect Register Write

C. 3.3 INTERFACING SOLUTIONS

4. 4.0 CONCLUSION

1.3 NM93CS Family

The NM93CS EEPROMs are available in 256-, 1024-, 2048-, and

4096-bit sizes. Making them different, they have two additional

functions, sequential read and user configurable write protection,

and don’t have either of the erase functions, ERASE and ERASE-

ALL as they are not needed. Like all of the CMOS EEPROMs,

these have self timed programming cycles and operate from a

single external supply of either 4.5V to 5.5V or 2.7V to 5.5V. In

these devices it is necessary to eliminate the erase cycles from the

code as they may adversely affect the performance of the device.

As these have additional functions, the instruction set includes a

total of 10 instructions, 3 that operate on the memory array, 2 that

deal with the basic write protection and 5 that deal with the user

configurable write protection. Refer to the NM93CS instruction set

table Table 2 for definitions of these instructions. As with the

NM93C family, there is a basic difference in instruction length

depending on memory size.

www.fairchildsemi.com

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