24VL024H
2K I
2
C
™
Serial EEPROM with Half-Array Write-Protect
Device Selection Table
Part Number
24VL024H
V
CC
Range
1.5 to 3.6V
Max. Clock
400 kHz
(1)
Description:
The Microchip Technology Inc. 24VL024H is a 2 Kbit
Serial Electrically Erasable PROM with operation
down to 1.5V. The device is organized as a single block
of 256 x 8-bit memory with a 2-wire serial interface.
Low-current design permits operation with typical
standby and active currents of only 1
μA
and 400
μA,
respectively. The device has a page write capability for
up to 16 bytes of data. Functional address lines allow
the connection of up to eight 24VL024H devices on the
same bus for up to 16 Kbits of contiguous EEPROM
memory. The device is available in the standard 8-pin
PDIP, 8-pin SOIC (150 mil), TSSOP, 2x3 TDFN and
MSOP packages.
Note 1:
100 kHz for V
CC
< 1.8V
Features:
• Single-Supply with Operation down to 1.5V
• Low-Power CMOS Technology:
- 400
μA
active current, maximum
- 1
μA
standby current, maximum
• 2-Wire Serial Interface Bus, I
2
C™ Compatible
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to eliminate Ground Bounce
• 100 kHz and 400 kHz Compatibility
• Page Write Buffer for up to 16 Bytes
• Self-Timed Write Cycle (including Auto-Erase)
• Hardware Write Protection for Half Array
(80h-FFh)
• Cascadable up to Eight Devices
• More than 1 Million Erase/Write Cycles
• ESD Protection > 4,000V
• Data Retention > 200 Years
• Factory Programming (QTP) Available
• 8-pin PDIP, SOIC, TSSOP, TDFN and MSOP
Packages
• Temperature Range:
- -20°C to +85°C
• Pb-Free and RoHS compliant
Block Diagram
A0 A1 A2
WP
HV Generator
Memory
Control
Logic
I/O
Control
Logic
XDEC
EEPROM
Array
SDA SCL
V
CC
V
SS
Write-Protect
Circuitry
YDEC
Sense Amp.
R/W Control
Package Types
PDIP, MSOP
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
A0
A1
A2
SOIC, TSSOP
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
SDA V
SS
TDFN
A0 1
A1 2
A2 3
V
SS
4
8 V
CC
7 WP
6 SCL
5 SDA
©
2008 Microchip Technology Inc.
DS22109A-page 1
24VL024H
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
V
CC
.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. V
SS
......................................................................................................... -0.6V to V
CC
+1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ..................................................................................................-20°C to +85°C
ESD protection on all pins
......................................................................................................................................................≥
4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
Electrical Characteristics:
V
CC
= +1.5V to 3.6V T
A
= -20°C to +85°C
Min.
—
0.7 V
CC
—
0.05 V
CC
Max.
—
—
0.3 V
CC
—
Units
—
V
V
V
—
—
—
(Note)
Conditions
DC CHARACTERISTICS
Param.
No.
D1
D2
D3
D4
Sym.
—
V
IH
V
IL
V
HYS
Characteristic
A0, A1, A2, SCL, SDA
and WP pins:
High-level input voltage
Low-level input voltage
Hysteresis of Schmitt
Trigger inputs
(SDA, SCL pins)
Low-level output voltage
Input leakage current
Output leakage current
Pin capacitance
(all inputs/outputs)
D5
D6
D7
D8
D9
D10
Note:
V
OL
I
LI
I
LO
C
IN
,
C
OUT
I
CC
Write
I
CCS
—
—
—
—
—
—
—
0.40
±1
±1
10
400
3
1
V
μA
μA
pF
μA
mA
μA
I
OL
= 3.0 mA @ V
CC
= 3.6V
I
OL
= 2.1 mA @ V
CC
= 2.5V
V
IN
= V
SS
or V
CC
, WP = V
SS
V
OUT
= V
SS
or V
CC
V
CC
= 3.6V
(Note)
T
A
= 25°C, f = 1 MHz
V
CC
= 3.6V, SCL = 400 kHz
V
CC
= 3.6V
V
CC
= 3.6V, SCL = SDA = V
CC
WP = V
SS
, A0, A1, A2 = V
SS
I
CC
Read Operating current
Standby current
This parameter is periodically sampled and not 100% tested.
DS22109A-page 2
©
2008 Microchip Technology Inc.
24VL024H
TABLE 1-2:
AC CHARACTERISTICS
Electrical Characteristics:
V
CC
= +1.5V to 3.6V T
A
= -20°C to +85°C
Characteristic
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
(Note 1)
SDA and SCL fall time
(Note 1)
Start condition hold time
Start condition setup time
Data input hold time
Data input setup time
Stop condition setup time
WP setup time
WP hold time
Output valid from clock
(Note 2)
Bus free time: Time the bus must
be free before a new transmis-
sion can start
Input filter spike suppression
(SDA and SCL pins)
Write cycle time (byte or page)
Endurance
Min.
—
—
4000
600
4700
1300
—
—
—
—
4000
600
4700
600
0
250
100
4000
600
4000
600
4700
600
—
—
1300
4700
—
—
1M
Max.
100
400
—
—
—
—
1000
300
1000
300
—
—
—
—
—
—
—
—
—
—
—
—
—
3500
900
—
—
50
5
—
Units
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions
1.5V
≤
V
CC
< 1.8V
1.8V
≤
V
CC
≤
3.6V
1.5V
≤
V
CC
< 1.8V
1.8V
≤
V
CC
≤
3.6V
1.5V
≤
V
CC
< 1.8V
1.8V
≤
V
CC
≤
3.6V
1.5V
≤
V
CC
< 1.8V
1.8V
≤
V
CC
≤
3.6V
1.5V
≤
V
CC
< 1.8V
1.8V
≤
V
CC
≤
3.6V
1.5V
≤
V
CC
< 1.8V
1.8V
≤
V
CC
≤
3.6V
1.5V
≤
V
CC
< 1.8V
1.8V
≤
V
CC
≤
3.6V
(Note 2)
1.5V
≤
V
CC
< 1.8V
1.8V
≤
V
CC
≤
3.6V
1.5V
≤
V
CC
< 1.8V
1.8V
≤
V
CC
≤
3.6V
1.5V
≤
V
CC
< 1.8V
1.8V
≤
V
CC
≤
3.6V
1.5V
≤
V
CC
< 1.8V
1.8V
≤
V
CC
≤
3.6V
1.5V
≤
V
CC
< 1.8V
1.8V
≤
V
CC
≤
3.6V
1.5V
≤
V
CC
< 1.8V
1.8V
≤
V
CC
≤
3.6V
(Note 1 and Note 3)
—
AC CHARACTERISTICS
Param.
Symbol
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
F
CLK
T
HIGH
T
LOW
T
R
T
F
T
HD
:
STA
T
SU
:
STA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
SU
:
WP
T
HD
:
WP
T
AA
T
BUF
15
16
17
T
SP
T
WC
—
ns
ms
cycles 25°C, V
CC
= 3.6V, Block mode
(Note 4)
Note 1:
Not 100% tested. C
B
= total capacitance of one bus line in pF.
2:
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3:
The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a T
I
specification for standard operation.
4:
This parameter is not tested but ensured by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at
www.microchip.com.
©
2008 Microchip Technology Inc.
DS22109A-page 3
24VL024H
FIGURE 1-1:
BUS TIMING DATA
5
2
D4
4
SCL
SDA
In
7
6
15
3
8
9
10
13
SDA
Out
(protected)
(unprotected)
14
WP
11
12
DS22109A-page 4
©
2008 Microchip Technology Inc.
24VL024H
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
Name
A0
A1
A2
V
SS
SDA
SCL
WP
V
CC
PIN FUNCTION TABLE
8-pin
PDIP
1
2
3
4
5
6
7
8
8-pin
SOIC
1
2
3
4
5
6
7
8
8-pin
TSSOP
1
2
3
4
5
6
7
8
8-pin
MSOP
1
2
3
4
5
6
7
8
8-pin
TDFN
1
2
3
4
5
6
7
8
Function
User Configurable Chip Select
User Configurable Chip Select
User Configurable Chip Select
Ground
Serial Data
Serial Clock
Write-Protect Input
+1.5V to 3.6V
2.1
SDA Serial Data
2.4
WP
This is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open drain
terminal. Therefore, the SDA bus requires a pull-up
resistor to V
CC
(typical 10 kΩ for 100 kHz, 2 kΩ for
400 kHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
WP is the hardware write-protect pin. It must be tied to
V
CC
or V
SS
. If tied to V
CC
, the hardware write protection
is enabled and will protect half of the array (80h-FFh).
If the WP pin is tied to V
SS
the hardware write
protection is disabled.
2.5
Noise Protection
2.2
SCL Serial Clock
The 24VL024H employs a V
CC
threshold detector cir-
cuit that disables the internal erase/write logic if the
V
CC
is below 1.2 volts at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits that suppress noise spikes to assure
proper device operation, even on a noisy bus.
The SCL input is used to synchronize the data transfer
to and from the device.
2.3
A0, A1, A2
The A0, A1 and A2 inputs are used by the 24VL024H
for multiple device operations. The levels on these
inputs are compared with the corresponding bits in the
slave address. The chip is selected if the compare is
true.
Up to eight 24VL024H devices may be connected to
the same bus by using different Chip Select bit
combinations. These inputs must be connected to
either V
CC
or V
SS
.
In most applications the chip address inputs, A0, A1
and A2, are hard-wired to logic ‘0’ or logic ‘1’. For
applications in which these pins are controlled by a
microcontroller or other programmable device, the chip
address pins must be driven to logic ‘0’ or logic ‘1’
before normal device operation can proceed.
©
2008 Microchip Technology Inc.
DS22109A-page 5
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