24AA515/24LC515/24FC515
512K I
2
C
™
CMOS Serial EEPROM
Device Selection Table
Part
Number
24AA515
24LC515
24FC515
†
V
CC
Range
1.8-5.5V
2.5-5.5V
2.5-5.5V
Max. Clock
Frequency
400 kHz
†
400 kHz
1 MHz
Temp.
Ranges
I
I
I
Reads may be sequential within address boundaries
0000h to 7FFFh and 8000h to FFFFh. Functional
address lines allow up to four devices on the same data
bus. This allows for up to 2 Mbits total system
EEPROM memory. This device is available in the
standard 8-pin plastic DIP and SOIJ packages.
100 kHz for V
CC
< 2.5V.
Package Type
PDIP
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
Features:
• Single Supply with Operation Down to 1.7V for
24AAXX Devices, 2.5V for 24LCXX Devices
• Low-Power CMOS Technology:
- Active current 500 uA, typical
- Standby current 100 nA, typical
• 2-Wire Serial Interface, I
2
C™ Compatible
• Cascadable up to Four Devices
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• Page Write Time 5 ms max.
• Self-Timed Erase/Write Cycle
• 64-Byte Page Write Buffer
• Hardware Write Protect
• ESD Protection >4000V
• More than 1 Million Erase/Write Cycles
• Data Retention >200 years
• Factory Programming Available
• Packages Include 8-lead PDIP, SOIJ
• Pb-Free and RoHS Compliant
• Temperature Ranges:
- Industrial (I): -40°C to +85°C
- Automotive (E):-40°C to +125°C
SOIJ
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
Block Diagram
A0A1
WP
HV Generator
I/O
Control
Logic
Memory
Control
Logic
XDEC
EEPROM
Array
Page Latches
I/O
Description:
The Microchip Technology Inc. 24AA515/24LC515/
24FC515 (24XX515*) is a 64K x 8 (512K bit) Serial
Electrically Erasable PROM, capable of operation
across a broad voltage range (1.7V to 5.5V). It has
been developed for advanced, low-power applications
such as personal communications or data acquisition.
This device has both byte write and page write capabil-
ity of up to 64 bytes of data. This device is capable of
both random and sequential reads.
SDA
SCL
YDEC
V
CC
V
SS
Sense AMP
R/W Control
*24XX515 is used in this document as a generic part number
for the 24AA515/24LC515/24FC515 devices.
©
2008 Microchip Technology Inc.
DS21673G-page 1
24AA515/24LC515/24FC515
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
V
CC
.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. V
SS
......................................................................................................... -0.6V to V
CC
+1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-40°C to +125°C
ESD protection on all pins
......................................................................................................................................................≥
4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
Industrial (I): V
CC
= +1.7V to 5.5V T
A
= -40°C to +85°C
Min.
Max.
Units
Conditions
DC CHARACTERISTICS
Param.
No.
Sym.
Characteristic
A0, A1, SCL, SDA and
WP pins:
D1
D2
D3
V
IH
V
IL
V
HYS
High-level input voltage
Low-level input voltage
Hysteresis of Schmitt
Trigger inputs
(SDA, SCL pins)
Low-level output voltage
Input leakage current
Output leakage current
Pin capacitance
(all inputs/outputs)
0.7 V
CC
—
0.05 V
CC
—
0.3 V
CC
0.2 V
CC
—
V
V
V
V
V
CC
≥
2.5V
V
CC
< 2.5V
V
CC
≥
2.5V
(Note)
D4
D5
D6
D7
D8
D9
Note:
V
OL
I
LI
I
LO
C
IN
,
C
OUT
I
CC
Write
Iccs
—
—
—
—
—
—
—
0.40
±1
±1
10
500
3
5
V
μA
μA
pF
μA
mA
μA
I
OL
= 3.0 mA @ V
CC
= 4.5V
I
OL
= 2.1 mA @ V
CC
= 2.5V
V
IN
= V
SS
or V
CC
, WP = V
SS
V
IN
= V
SS
or V
CC
, WP = V
CC
V
OUT
= V
SS
or V
CC
V
CC
= 5.0V
(Note)
T
A
= 25°C, F
CLK
= 1 MHz
V
CC
= 5.5V, SCL = 400 kHz
V
CC
= 5.5V
SCL = SDA = V
CC
= 5.5V
A0, A1, WP = V
SS
, A2 = V
CC
I
CC
Read Operating current
Standby current
This parameter is periodically sampled and not 100% tested.
DS21673G-page 2
©
2008 Microchip Technology Inc.
24AA515/24LC515/24FC515
TABLE 1-2:
AC CHARACTERISTICS
Industrial (I):
Characteristic
Clock frequency
Min.
—
—
—
4000
600
500
4700
1300
500
—
—
—
—
—
4000
600
250
4700
600
250
0
250
100
100
4000
600
250
4000
600
600
4700
1300
1300
—
—
—
4700
1300
500
10 + 0.1C
B
AC CHARACTERISTICS
Param.
No.
1
Sym.
F
CLK
V
CC
= +1.7V to 5.5V T
A
= -40°C to +85°C
Max.
100
400
1000
—
—
—
—
—
—
1000
300
300
300
100
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3500
900
400
—
—
—
250
250
50
5
—
Units
kHz
Conditions
1.7V
≤
V
CC
≤
2.5V
2.5V
≤
V
CC
≤
5.5V
2.5V
≤
V
CC
≤
5.5V (24FC515 only)
1.7V
≤
V
CC
≤
2.5V
2.5V
≤
V
CC
≤
5.5V
2.5V
≤
V
CC
≤
5.5V (24FC515 only)
1.7V
≤
V
CC
≤
2.5V
2.5V
≤
V
CC
≤
5.5V
2.5V
≤
V
CC
≤
5.5V (24FC515 only)
1.7V
≤
V
CC
≤
2.5V
2.5V
≤
V
CC
≤
5.5V
2.5V
≤
V
CC
≤
5.5V (24FC515 only)
All except, 24FC515
2.5V
≤
V
CC
≤
5.5V (24FC515 only)
1.7V
≤
V
CC
≤
2.5V
2.5V
≤
V
CC
≤
5.5V
2.5V
≤
V
CC
≤
5.5V (24FC515 only)
1.7V
≤
V
CC
≤
2.5V
2.5V
≤
V
CC
≤
5.5V
2.5V
≤
V
CC
≤
5.5V (24FC515 only)
(Note 2)
1.7V
≤
V
CC
≤
2.5V
2.5V
≤
V
CC
≤
5.5V
2.5V
≤
V
CC
≤
5.5V (24FC515 only)
1.7V
≤
V
CC
≤
2.5V
2.5V
≤
V
CC
≤
5.5V
2.5V
≤
V
CC
≤
5.5V (24FC515 only)
1.7V
≤
V
CC
≤
2.5V
2.5V
≤
V
CC
≤
5.5V
2.5V
≤
V
CC
≤
5.5V (24FC515 only)
1.7V
≤
V
CC
≤
2.5V
2.5V
≤
V
CC
≤
5.5V
2.5V
≤
V
CC
≤
5.5V (24FC515 only)
1.7V
≤
V
CC
≤
2.5V
2.5V
≤
V
CC
≤
5.5V
2.5V
≤
V
CC
≤
5.5V (24FC515 only)
1.7V
≤
V
CC
≤
2.5V
2.5V
≤
V
CC
≤
5.5V
2.5V
≤
V
CC
≤
5.5V (24FC515 only)
All except, 24FC515
(Note 1)
24FC515
(Note 1)
All except, 24FC515
(Notes 1 and 3)
2
T
HIGH
Clock high time
ns
3
T
LOW
Clock low time
ns
4
T
R
SDA and SCL rise time
(Note 1)
SDA and SCL fall time
(Note 1)
ns
5
6
T
F
ns
ns
T
HD
:
STA
Start condition hold time
7
T
SU
:
STA
Start condition setup time
ns
8
9
T
HD
:
DAT
Data input hold time
T
SU
:
DAT
Data input setup time
ns
ns
10
T
SU
:
STO
Stop condition setup time
ns
11
T
SU
:
WP
WP setup time
ns
12
T
HD
:
WP
WP hold time
ns
13
T
AA
Output valid from clock
(Note 2)
Bus free time: Time the bus
must be free before a new
transmission can start
Output fall time from V
IH
minimum to V
IL
maximum
C
B
≤
100 pF
Input filter spike suppression
(SDA and SCL pins)
Write cycle time (byte or page)
Endurance
ns
14
T
BUF
ns
15
T
OF
ns
16
17
18
T
SP
T
WC
Note 1:
2:
3:
4:
—
—
1M
ns
ms
cycles
25°C
(Note 4)
Not 100% tested. C
B
= total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs which provide improved noise spike
suppression. This eliminates the need for a TI specification for standard operation.
This parameter is not tested but established by characterization. For endurance estimates in a specific application,
please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.
©
2008 Microchip Technology Inc.
DS21673G-page 3
24AA515/24LC515/24FC515
FIGURE 1-1:
BUS TIMING DATA
5
D4
4
2
SCL
SDA
IN
7
6
16
3
8
9
10
13
SDA
OUT
(protected)
(unprotected)
14
WP
11
12
DS21673G-page 4
©
2008 Microchip Technology Inc.
24AA515/24LC515/24FC515
2.0
PIN DESCRIPTIONS
2.4
Serial Clock (SCL)
The descriptions of the pins are listed in Table 2-1.
This input is used to synchronize the data transfer from
and to the device.
TABLE 2-1:
A0
A1
A2
1
2
3
PIN FUNCTION TABLE
Function
User Configurable Chip Select
User Configurable Chip Select
Non-Configurable Chip Select.
This pin must be hard wired to
logical
1
state (V
CC
). Device
will not operate with this pin
left floating or held to logical
0
(V
SS
).
Ground
Serial Data
Serial Clock
Write-Protect Input
+1.7 to 5.5V (24AA515)
+2.5 to 5.5V (24LC515)
+2.5 to 5.5V (24FC515)
Name PDIP SOIJ
1
2
3
2.5
Write-Protect (WP)
This pin must be connected to either V
SS
or V
CC
. If tied
to V
SS
, write operations are enabled. If tied to V
CC
,
write operations are inhibited but read operations are
not affected.
3.0
FUNCTIONAL DESCRIPTION
V
SS
SDA
SCL
WP
V
CC
4
5
6
7
8
4
5
6
7
8
The 24XX515 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device
receiving data as a receiver. The bus must be
controlled by a master device which generates the
Serial Clock (SCL), controls the bus access, and
generates the Start and Stop conditions while the
24XX515 works as a slave. Both master and slave can
operate as a transmitter or receiver, but the master
device determines which mode is activated.
2.1
A0, A1 Chip Address Inputs
The A0, A1 inputs are used by the 24XX515 for multiple
device operations. The levels on these inputs are
compared with the corresponding bits in the slave
address. The chip is selected if the compare is true.
Up to four devices may be connected to the same bus
by using different Chip Select bit combinations. In most
applications, the chip address inputs A0 and A1 are
hard-wired to logic ‘0’ or logic ‘1’. For applications in
which these pins are controlled by a microcontroller or
other programmable device, the chip address pins
must be driven to logic ‘0’ or logic ‘1’ before normal
device operation can proceed.
2.2
A2 Chip Address Input
The A2 input is non-configurable Chip Select. This pin
must be tied to V
CC
in order for this device to operate.
2.3
Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open-
drain terminal, therefore, the SDA bus requires a pull-
up resistor to V
CC
(typical 10 kΩ for 100 kHz, 2 kΩ for
400 kHz and 1 MHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
©
2008 Microchip Technology Inc.
DS21673G-page 5
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