VL-821
CMOS Crystal Oscillator
Previous Vectron Model VCS3
VL-821
Description
Vectron’s VL-821 Crystal Oscillator (XO) is a quartz stabilized square wave generator with a CMOS output, operating o either a
1.8, 2.5, or 3.3 volt supply. The VL-821 utilizes a high performance, low frequency quartz resonator followed by a custom ASIC to
synthesize the output frequency.
Features
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Applications
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SONET/SDH/DWDM
Ethernet, GE, SynchE
Storage Area Networking
Digital Video
Broadband Access
Microprocessors/DSP/FPGA
Quick delivery
CMOS Output
3.2mm x 2.5mm x 1.2mm
Output frequencies to 200.00 MHz
Tri-state output for the board test and debug
-10/70°C or -40/85°C operating temperature
Gold over nickel contact pads
Hermetically Sealed SMD Package
Product is compliant to RoHS directive
and fully compatible with lead free assembly
Block Diagram
V
DD
Crystal
Output
Osc
PLL
E/D
Gnd
Page1
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Performance Speci cations
Table 1. Electrical Performance, 3.3V Option
Parameter
Operating Supply Voltage
1
Absolute Maximum Operating Voltage
Supply Current, Output Enabled
<30 MHz
30.01 to 75 MHz
75.01 to 133 MHz
133.01 to 200 MHz
Supply Current, Output Disabled
Frequency
Stability
4
, (Ordering Option)
Outputs
Output Logic Levels
Output Logic High
2
Output Logic Low
2
Output Logic High Drive
Output Logic Low Drive
Output Rise /Fall Time
2
, fo≤10MHz
fo>10MHz
Duty Cycle
3
Output Enable/Disable
5
Output Enable
Output Disable
Internal Pull-Up Resistor
Start-Up Time
Operating Temp, (Ordering Option)
1]
2]
3]
4]
5]
Symbol
V
DD
I
DD
Min
Supply
2.97
-0.05
Typical
3.3
Maximum
3.63
5.0
10
15
20
25
Units
V
V
mA
mA
mA
mA
uA
MHz
ppm
I
DD
Frequency
f
O
1.000
±25, ±50, ±100
15
200.00
V
OH
V
OL
I
OH
I
OL
t
R
/t
F
SYM
0.9*V
DD
0.1*V
DD
8
8
3
2
45
Enable/Disable
50
55
V
V
mA
mA
ns
ns
%
V
IH
V
IL
t
SU
T
OP
0.7*V
DD
0.3V*
DD
100
2
-10/70 or -40/85
V
V
K
ms
°C
A 0.01 uF and a 0.1uF capacitor should be located as close to the supply as possible (to ground). V
DD
supply ramp should be <100 msec
.
Figure 2 de nes these parameters. Figure 1 illustrates the operating conditions under which these parameters are tested and speci ed.
Symmetry is measured de ned as On Time/Period.
Includes calibration tolerance, operating temperature, supply voltage variations, aging and shock and vibration (not under operation).
Output will be enabled if the Enable/Disable is left open. E/D should be powered up after V
DD
.
t
R
I
DD
+
V
DD
4
.1µF
.01µF
1
+
Period
Fig 1: Test Circuit
Fig 2: Waveform
t
F
V
OH
3
2
15pF
50%
V
OL
On Time
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Page2
Performance Speci cations
Table 2. Electrical Performance, 2.5V Option
Parameter
Operating Supply Voltage
1
Absolute Maximum Opertaing Voltage
Supply Current, Output Enabled
<30 MHz
30.01 to 75 MHz
75.01 to 166 MHz
Supply Current, Output Disabled
Frequency
Stability
4
,
(Ordering
Option)
Outputs
Output Logic Levels
Output Logic High
2
Output Logic Low
2
Output Logic High Drive
Output Logic Low Drive
Output Rise /Fall Time
2
, fo≤10MHz
fo>10MHz
Duty Cycle
3
Output Enable/Disable
5
Output Enable
Output Disable
Internal Pull-Up Resistor
Start-Up Time
Operating Temp, (Ordering Option)
1]
2]
3]
4]
5]
Symbol
V
DD
I
DD
Min
Supply
2.25
-0.5
Typical
2.5
Maximum
2.75
5
8.0
10.0
15.0
Units
V
V
mA
mA
mA
uA
MHz
ppm
I
DD
Frequency
f
O
1.000
±25, ±50, ±100
15
166.000
V
OH
V
OL
I
OH
I
OL
t
R
/t
F
SYM
0.9*V
DD
0.1*V
DD
8
8
4
3
45
Enable/Disable
50
55
V
V
mA
mA
ns
ns
%
V
V
IH
V
IL
t
SU
T
OP
0.7*V
DD
0.3*V
DD
100
2
-10/70 or -40/85
K
ms
°C
A 0.01 uF and a 0.1uF capacitor should be located as close to the supply as possible (to ground). V
DD
supply ramp should be <100 msec
.
Figure 2 de nes these parameters. Figure 1 illustrates the operating conditions under which these parameters are tested and speci ed.
Symmetry is measured de ned as On Time/Period.
Includes calibration tolerance, operating temperature, supply voltage variations, aging and shock and vibration (not under operation).
Output will be enabled if the Enable/Disable is left open. E/D should be powered up after V
DD
.
t
R
I
DD
+
4
.1µF
.01µF
I
C
V
C
Fig 1: Test Circuit
t
F
V
OH
3
2
15pF
1
+
50%
V
OL
On Time
Period
Fig 2: Waveform
V
DD
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Page3
Performance Speci cations
Table 3. Electrical Performance, 1.8V Option
Parameter
Operating Supply Voltage
1
Absolute Maximum Voltage
Supply Current, Output Enabled
<30 MHz
30.01 to 75 MHz
75.01 to 133 MHz
Supply Current, Output Disabled
Frequency
Stability
4
, (Ordering Option)
Outputs
Output Logic Levels
Output Logic High
2
Output Logic Low
2
Output Logic High Drive
Output Logic Low Drive
Output Rise /Fall Time
2,
, fo ≤10MHz
fo>10MHz
Duty Cycle
3
Output Enable/Disable
5
Output Enable
Output Disable
Internal Pull-Up Resistor
Start-Up Time
Operating Temp, (Ordering Option)
1]
2]
3]
4]
5]
Symbol
V
DD
I
DD
Min
Supply
1.62
-0.5
Typical
1.8
Maximum
1.98
3.6
6
8
12
Units
V
V
mA
I
DD
Frequency
f
O
1.000
±25, ±50, ±100
15
133.00
uA
MHz
ppm
V
OH
V
OL
I
OH
I
OL
t
R
/t
F
SYM
0.9*V
DD
0.1*V
DD
8
8
5
4
45
Enable/Disable
50
55
V
V
mA
mA
ns
ns
%
V
IH
V
IL
t
SU
T
OP
0.7*V
DD
0.3*V
DD
100
2
-10/70 or -40/85
V
V
K
ms
°C
A 0.01 uF and a 0.1uF capacitor should be located as close to the supply as possible (to ground). V
DD
supply ramp should be <100 msec
.
Figure 2 de nes these parameters. Figure 1 illustrates the operating conditions under which these parameters are tested and speci ed.
Symmetry is measured de ned as On Time/Period.
Includes calibration tolerance, operating temperature, supply voltage variations, aging and shock and vibration (not under operation).
Output will be enabled if the Enable/Disable is left open. E/D should be powered up after V
DD
.
t
R
I
DD
+
V
DD
4
.1µF
.01µF
I
C
V
C
Fig 1: Test Circuit
t
F
V
OH
3
2
15pF
50%
V
OL
On Time
Period
Fig 2: Waveform
1
+
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Page4
Outline Drawing & Pad Layout
FFMFFF
YWW T
Table 4. Pin Out
Pin
1
2
3
4
Symbol
E/D
GND
f
O
Function
Enable Disable
Case and Electrical Ground
Output Frequency
Power Supply Voltage
V
DD
Reliability
VI quali cation includes aging at various extreme temperatures, shock and vibration, temperature cycling, and IR re ow
simulation. The VL-821 family is capable of meeting the following quali cation tests:
Table 5. Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Temperature Cycle
Solderability
Gross and Fine Leak
Resistance to Solvents
Moisture Sensitivity Level
Conditions
MIL-STD-883, Method 2002
MIL-STD-883, Method 2007
MIL-STD-883, Method 1010
MIL-STD-883, Method 2003
MIL-STD-883, Method 1014
MIL-STD-883, Method 2015
MSL 1
Contact Pads
Gold over Nickel
Typical Characteristics - Phase Noise and Gain Curve
Although ESD protection circuitry has been designed into the VL-821 proper precautions should be taken when handling
and mounting. VI employs a human body model (HBM) and a charged device model (CDM) for ESD susceptibility testing
and design protection evaluation.
Table 6. ESD Ratings
Model
Human Body Model
Charged Device Model
Minimum
1500V
1000V
Conditions
MIL-STD-883, Method 3115
JESD 22-C101
Stresses in excess of the absolute maximum ratings can permanently damage the device. Functional operation is not
implied at these or any other conditions in excess of conditions represented in the operational sections of this datasheet.
Exposure to absolute maximum ratings for extended periods may adversely a ect device reliability. Permanent damage is
also possible if E/D is applied before V
DD
.
Table 7. Absolute Maximum Ratings
Parameter
Storage Temperature
Soldering Temp/Time
Symbol
TS
T
LS
Ratings
-55 to 125
260 / 20
Unit
°C
°C / sec
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Page5
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