PHM18NQ15T
TrenchMOS™ standard level FET
Rev. 02 — 20 August 2004
M3D879
Product data
1. Product profile
1.1 Description
N-channel enhancement mode field-effect transistor in a plastic package using
TrenchMOS™ technology.
1.2 Features
s
SOT96 (SO-8) footprint compatible
s
Surface mounted package
s
Low thermal resistance
s
Low profile.
1.3 Applications
s
DC-to-DC converter primary side
switch
s
Portable equipment applications.
1.4 Quick reference data
s
V
DS
≤
150 V
s
P
tot
≤
62.5 W
s
I
D
≤
19 A
s
R
DSon
≤
75 mΩ.
2. Pinning information
Table 1:
Pin
1,2,3
4
5,6,7,8
mb
Pinning - SOT685-1 (QLPAK), simplified outline and symbol
Description
source (s)
gate (g)
drain (d)
mounting base;
connected to drain (d)
1
4
Simplified outline
Symbol
d
mb
g
mbb076
8
Bottom view
5
MBL585
s
SOT685-1 (QLPAK)
[1]
Shaded area indicates pin 1 identifier.
Philips Semiconductors
PHM18NQ15T
TrenchMOS™ standard level FET
3. Ordering information
Table 2:
Ordering information
Package
Name
PHM18NQ15T
QLPAK
Description
HVSON8: plastic thermal enhanced very thin small outline package;
no leads; 8 terminals; 6 x 5 x 0.85 mm
Version
SOT685-1
Type number
4. Limiting values
Table 3:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
I
S
I
SM
drain-source voltage (DC)
drain-gate voltage (DC)
gate-source voltage (DC)
drain current (DC)
peak drain current
total power dissipation
storage temperature
junction temperature
source (diode forward) current (DC) T
mb
= 25
°C
peak source (diode forward) current T
mb
= 25
°C;
pulsed; t
p
≤
10
µs
unclamped inductive load; I
D
= 9.9 A;
t
p
= 0.16 ms; V
DD
≤
150 V; V
GS
= 10 V;
starting T
j
= 25
°C
T
mb
= 25
°C;
V
GS
= 10 V;
Figure 2
and
3
T
mb
= 100
°C;
V
GS
= 10 V;
Figure 2
T
mb
= 25
°C;
pulsed; t
p
≤
10
µs;
Figure 3
T
mb
= 25
°C;
Figure 1
Conditions
25
°C ≤
T
j
≤
150
°C
25
°C ≤
T
j
≤
150
°C;
R
GS
= 20 kΩ
Min
-
-
-
-
-
-
-
−55
−55
-
-
-
Max
150
150
±20
19
12
76
62.5
+150
+150
19
60
170
Unit
V
V
V
A
A
A
W
°C
°C
A
A
mJ
Source-drain diode
Avalanche ruggedness
E
DS(AL)S
non-repetitive drain-source
avalanche energy
9397 750 13865
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 02 — 20 August 2004
2 of 12
Philips Semiconductors
PHM18NQ15T
TrenchMOS™ standard level FET
120
P
der
(%)
80
03aa15
120
I
der
(%)
03aa23
80
40
40
0
0
50
100
150
T
mb
(°C)
200
0
0
50
100
150
200
T
mb
(°C)
P
tot
P
der
=
----------------------
×
100%
-
P
°
tot
(
25 C
)
V
GS
≥
10 V
I
D
I
der
=
-------------------
×
100%
I
°
D
(
25 C
)
Fig 1. Normalized total power dissipation as a
function of mounting base temperature.
10
2
I
D
(A)
10
Limit R
DSon
= V
DS
/ I
D
Fig 2. Normalized continuous drain current as a
function of mounting base temperature.
003aaa355
t
p
= 10
µs
100
µs
DC
1 ms
10 ms
1
10
-1
10
-2
1
10
10
2
V
DS
(V)
10
3
T
mb
= 25
°C;
I
DM
is single pulse.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 13865
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 02 — 20 August 2004
3 of 12
Philips Semiconductors
PHM18NQ15T
TrenchMOS™ standard level FET
5. Thermal characteristics
Table 4:
R
th(j-mb)
Thermal characteristics
Conditions
Min Typ Max Unit
-
-
2
K/W
thermal resistance from junction to mounting base
Figure 4
Symbol Parameter
5.1 Transient thermal impedance
10
Zth(j-mb)
(K/W)
1
δ
= 0.5
0.2
0.1
10-1
0.05
0.02
03aj27
10-2
single pulse
P
δ
=
tp
T
tp
T
10-3
10-5
10-4
10-3
10-2
10-1
t
tp (s)
1
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.
9397 750 13865
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 02 — 20 August 2004
4 of 12
Philips Semiconductors
PHM18NQ15T
TrenchMOS™ standard level FET
6. Characteristics
Table 5:
Characteristics
T
j
= 25
°
C unless otherwise specified.
Symbol Parameter
Static characteristics
V
(BR)DSS
drain-source breakdown voltage
I
D
= 250
µA;
V
GS
= 0 V
T
j
= 25
°C
T
j
=
−55 °C
V
GS(th)
gate-source threshold voltage
I
D
= 1 mA; V
DS
= V
GS
;
Figure 9
T
j
= 25
°C
T
j
= 150
°C
T
j
=
−55 °C
I
DSS
drain-source leakage current
V
DS
= 120 V; V
GS
= 0 V
T
j
= 25
°C
T
j
= 150
°C
I
GSS
R
DSon
gate-source leakage current
drain-source on-state resistance
V
GS
=
±10
V; V
DS
= 0 V
V
GS
= 10 V; I
D
= 12 A;
Figure 7
and
8
T
j
= 25
°C
T
j
= 150
°C
V
GS
= 5 V; I
D
= 3 A;
Figure 7
and
8
Dynamic characteristics
Q
g(tot)
Q
gs
Q
gd
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
V
SD
t
rr
Q
r
total gate charge
gate-source charge
gate-drain (Miller) charge
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
turn-off delay time
fall time
source-drain (diode forward) voltage I
S
= 5 A; V
GS
= 0 V;
Figure 11
reverse recovery time
recovered charge
I
S
= 5 A; dI
S
/dt =
−100
A/µs; V
R
= 90 V;
V
GS
= 0 V
V
DD
= 75 V; I
D
= 5 A; V
GS
= 10 V; R
G
= 6
Ω
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz;
Figure 12
I
D
= 5 A; V
DD
= 75 V; V
GS
= 10 V;
Figure 13
-
-
-
-
-
-
-
-
-
-
-
-
-
26.4
3.9
8.8
187
61
12
11
35
18
0.76
87
162
-
-
-
-
-
-
-
-
-
1.2
-
-
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
V
ns
nC
-
-
-
56
129
60
75
173
80
mΩ
mΩ
mΩ
-
-
-
-
-
10
1
100
100
µA
µA
nA
2
1.2
-
3
-
-
4
-
4.4
V
V
V
150
134
-
-
-
-
V
V
Conditions
Min
Typ
Max
Unit
1150 -
Source-drain diode
9397 750 13865
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 02 — 20 August 2004
5 of 12
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