EEWORLDEEWORLDEEWORLD

Part Number

Search

5SGXMA7K2F35I2

Description
Field Programmable Gate Array, 622000-Cell, CMOS, PBGA1152,
CategoryProgrammable logic devices    Programmable logic   
File Size388KB,22 Pages
ManufacturerIntel
Websitehttp://www.intel.com/
Download Datasheet Parametric View All

5SGXMA7K2F35I2 Overview

Field Programmable Gate Array, 622000-Cell, CMOS, PBGA1152,

5SGXMA7K2F35I2 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Reach Compliance Codecompli
JESD-30 codeS-PBGA-B1152
Number of entries432
Number of logical units622000
Output times432
Number of terminals1152
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Encapsulate equivalent codeBGA1152,34X34,40
Package shapeSQUARE
Package formGRID ARRAY
power supply0.9,1.5,2.5,2.5/3,1.2/3 V
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
surface mountYES
technologyCMOS
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Base Number Matches1
1. Stratix V Device Family Overview
February 2012
SV51001-2.3
SV51001-2.3
This chapter provides an overview of the Stratix
®
V devices and their features. Many
of these devices and features are enabled in the Quartus
®
II software version 11.1. The
remaining devices and features will be enabled in future versions of the Quartus II
software.
f
To find out more about the upcoming Stratix V devices and features, refer to the
Stratix V Upcoming Device Features
document.
Altera’s 28-nm Stratix V FPGAs include innovations such as an enhanced core
architecture, integrated transceivers up to 28.05 gigabits per second (Gbps), and a
unique array of integrated hard intellectual property (IP) blocks. With these
innovations, Stratix V FPGAs deliver a new class of application-targeted devices
optimized for:
Bandwidth-centric applications and protocols, including PCI Express
®
(PCIe
®
)
Gen3
Data-intensive applications for 40G/100G and beyond
High-performance, high-precision digital signal processing (DSP) applications
Stratix V devices are available in four variants (GT, GX, GS, and E), each targeted for a
different set of applications. For higher volume production, you can prototype with
Stratix V FPGAs and use the low-risk, low-cost path to HardCopy
®
V ASICs.
Stratix V Family Variants
Stratix V GT
devices, with both 28.05-Gbps and 12.5-Gbps transceivers, are
optimized for applications that require ultra-high bandwidth and performance in
areas such as 40G/100G/400G optical communications systems and optical test
systems. 28.05-Gbps and 12.5-Gbps transceivers are also known as GT and GX
channels, respectively.
Stratix V GX
devices offer up to 66 integrated 14.1-Gbps transceivers supporting
backplanes and optical modules. These devices are optimized for high-performance,
high-bandwidth applications such as 40G/100G optical transport, packet processing,
and traffic management found in wireline, military communications, and network
test equipment markets.
Stratix V GS
devices have an abundance of variable precision DSP blocks, supporting
up to 3,926 18x18 or 1,963 27x27 multipliers. In addition, Stratix V GS devices offer
integrated 14.1-Gbps transceivers, which support backplanes and optical modules.
These devices are optimized for transceiver-based DSP-centric applications found in
wireline, military, broadcast, and high-performance computing markets.
© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at
www.altera.com/common/legal.html.
Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Stratix V Device Handbook
Volume 1: Overview and Datasheet
February 2012
Subscribe
430 Assembly Help!
149 assembly program.Q03142 MOV.W 0xD0E4, R6Q03146 AND.W 0xD2E0, R6Q0314A BIS.W R6, 0xD2BCWhat do the above addresses 0xD0E4, 0xD2E0, 0xD2BC mean? In 149, the address range of RAM is 0200H-09FFH and t...
killhill Microcontroller MCU
How to lay out code dependencies to make the program easy to modify
I just modified a program and need to modify the parameters of a variable, which will affect other functions. If we continue to link them, we will need to modify many things, and it is easy to miss im...
zmsxhy Embedded System
[OpenCV Getting Started Tutorial 11] Morphological Image Processing (II): Opening, Closing, Morphological Gradient, Vertex...
[i=s]This post was last edited by Rambo on 2017-12-27 14:32[/i] [indent][font="][size=14px]In the previous article, we focused on the two most basic morphological operations, erosion and dilation. Usi...
兰博 Embedded System
No matter how hard life is, I will be strong!
No matter how hard life is, I will be strong!...
wlygsgs Talking
Do you know that there are some particularities about mouse pads?
From using the scroll wheel to now, I have never paid close attention to it. Nowadays, most mice are optical, except for those who are nostalgic. So are there any particular requirements for mouse pad...
wangfuchong Talking
The Linux Foundation and the RISC-V Foundation work together to promote open source chips
Linux is the world's most well-known and important open source project, and RISC-V is an open source CPU instruction set that has emerged in recent years. The RISC-V Foundation is a non-profit organiz...
木犯001号 FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2232  124  2264  2003  1983  45  3  46  41  40 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号