W49F002U
256K
×
8 CMOS FLASH MEMORY
GENERAL DESCRIPTION
The W49F002U is a 2-megabit, 5-volt only CMOS flash memory organized as 256K
×
8 bits. The
device can be programmed and erased in-system with a standard 5V power supply. A 12-volt V
PP
is
not required. The unique cell architecture of the W49F002U results in fast program/erase operations
with extremely low current consumption (compared to other comparable 5-volt flash memory products).
The device can also be programmed and erased using standard EPROM programmers.
FEATURES
•
Single 5-volt operations:
−
5-volt Read
−
5-volt Erase
−
5-volt Program
Fast Program operation:
−
Byte-by-Byte programming: 35
µS
(typ.)
Fast Erase operation: 100 mS (typ.)
Fast Read access time: 70/90/120 nS
Endurance: 10K cycles (typ.)
Ten-year data retention
Hardware data protection
One 16K byte Boot Block with Lockout
protection
Two 8K byte Parameter Blocks
•
•
Two Main Memory Blocks (96K, 128K) Bytes
Low power consumption
Active current: 25 mA (typ.)
Standby current: 20
µA
(typ.)
Automatic program and erase timing with
internal V
PP
generation
End of program or erase detection
−
Toggle bit
−
Data polling
−
−
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Latched address and data
TTL compatible I/O
JEDEC standard byte-wide pinouts
Available packages: 32-pin DIP, 32-pin
STSOP (8 mm
×
14 mm), 32-pin TSOP
(8 mm
×
20 mm) and 32-pin-PLCC
-1-
Publication Release Date: February 21, 2002
Revision A6
W49F002U
PIN CONFIGURATIONS
BLOCK DIAGRAM
VDD
#RESET
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
V
DD
#WE
A17
A14
A13
A8
A9
A11
#OE
A10
#CE
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
#CE
#OE
#WE
#RESET
CONTROL
OUTPUT
BUFFER
DQ0
.
.
DQ7
32-pin
DIP
26
25
24
23
22
21
20
19
18
17
BOOT BLOCK
16K BYTES
A0
.
DECODER
PARAMETER
BLOCK1
8K BYTES
PARAMETER
BLOCK2
8K BYTES
MAIN MEMORY
BLOCK1
96K BYTES
3FFFF
3C000
3BFFF
3A000
39FFF
A
1
2
4
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
5
6
7
8
9
10
11
12
13
A
1
5
3
A
1
6
2
#
R
E
S
E
T
.
V #
D W
D E
A
1
7
A17
1 32 31 30
29
28
27
A14
A13
A8
A9
A11
#OE
A10
#CE
DQ7
38000
37FFF
32-pin
PLCC
26
25
24
23
22
21
20000
MAIN MEMORY 1FFFF
BLOCK2
00000
128K BYTES
14 15 16 17 18 19 20
D D
Q Q
1 2
V
s
s
D
Q
3
D
Q
4
D
Q
5
D
Q
6
PIN DESCRIPTION
A11
A9
A8
A13
A14
A17
#WE
V
DD
#RESET
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
#OE
A10
#CE
DQ7
DQ6
DQ5
DQ4
DQ3
Vss
DQ2
DQ1
DQ0
A0
A1
A2
A3
SYMBOL
#RESET
A0
−
A17
DQ0
−
DQ7
#CE
#OE
#WE
V
DD
V
SS
Reset
PIN NAME
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
32-pin
TSOP
A16
A15
A12
A7
A6
A5
A4
-2-
W49F002U
FUNCTIONAL DESCRIPTION
Device Operation
Read Mode
The read operation of the W49F002U is controlled by #CE and #OE, both of which have to be low for
the host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the chip
is de-selected and only standby power will be consumed. #OE is the output control and is used to gate
data from the output pins. The data bus is in high impedance state when either #CE or #OE is high.
Refer to the timing waveforms for details.
Write Mode
Device erase and program are accomplished via the command register. The content of the register
serves as inputs to the internal state machine. The state machine outputs dictate the function of the
device.
The command register itself does not occupy any addressable memory location. The register is a latch
used to store the commands, along with the address and data information needed to execute the
command. The command register is written to bring #WE to logic low state when #CE is at logic low
state and #OE is at logic high state. Addresses are latched on the falling edge of #WE or #CE,
whichever happens later; while data is latched on the rising edge of #WE or #CE, whichever happens
first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing
parameters.
Standby Mode
There are two ways to implement the standby mode on the W49F002U device, both using the #CE pin.
A CMOS standby mode is achieved with the
#CE input held at V
DD
-0.3V. Under this condition the current
is typically reduced to less than 100
µA.
A TTL standby mode is achieved with the #CE pin held at V
IH
.
Under this condition the current is typically reduced to less than 3 mA.
In the standby mode the outputs are in the high impedance state, independent of the #OE input.
Output Disable Mode
With the #OE input at a logic high level (V
IH
), output from the device is disabled. This will cause the
output pins to be in a high impedance state.
Auto-select Mode
The auto-select mode allows the reading of a binary code from the device and will identify its
manufacturer and type. This mode is intended to be used by programming equipment for the purpose
of automatically matching the device to be programmed with its corresponding programming algorithm.
This mode is functional over the entire temperature range of the device.
To activate this mode, the programming equipment must force V
ID
(11.5V to 12.5V) on address pin A9.
Two identifier bytes may then be sequenced from the device outputs by toggling address A0 from V
IL
to V
IH
. All addresses are don′t cares except A0 and A1 (see "Auto-select Codes").
Note: The
hardware SID read function is not included in all parts; please refer to Ordering Information for
details.
Publication Release Date: February 21, 2002
Revision A6
-3-
W49F002U
The manufacturer and device codes may also be read via the command register; i.e., the W49F002U
is erased or programmed in a system without access to high voltage on the A9 pin. The command
sequence is illustrated in "Auto-select Codes".
Byte 0 (A0 = V
IL
) represents the manufacturer′s code (Winbond = DAh) and byte 1 (A0 = V
IH
) the
device identifier code (W49F002U = 0Bh,). All identifiers for manufacturer and device will exhibit odd
parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing the
Auto-select, A1 must be V
IL
.
Reset Mode: Hardware Reset
The #RESET pin provides a hardware method of resetting the device to reading array data. When the
system drives the #RESET pin low for at least a period of t
RP
, the device immediately terminates any
operation in progress, tri-states all data output pins, and ignores all read/write attempts for the duration
of the #RESET pulse. The device also resets the internal state machine to reading array data. The
operation that was interrupted should be reinitiated once the device is ready to accept another
command sequence, to ensure data integrity.
Current is reduced for the duration of the #RESET pulse. When #RESET is held at V
IL
, the device
enters the TTL standby mode; if #RESET is held at Vss, the device enters the CMOS standby mode.
The #RESET pin may be tied to the system reset circuitry. A system reset would thus also reset the
Flash memory, enabling the system to read the boot-up firmware from the Flash memory.
Data Protection
The W49F002U is designed to offer protection against accidental erasure or programming caused by
spurious system level signals that may exist during power transitions. During power up the device
automatically resets the internal state machine in the Read mode. Also, with its control register
architecture, alteration of the memory contents only occurs after successful completion of specific
multi-bus cycle command sequences. The device also incorporates several features to prevent
inadvertent write cycles resulting from V
DD
power-up and power-down transitions or system noise.
Low V
DD
Inhibit
To avoid initiation of a write cycle during V
DD
power-up and power-down, the W49F002U locks out
when V
DD
< 2.5V. The write and read operations are inhibited when V
DD
is less than 2.5V typical. The
W49F002U ignores all write and read operations until V
DD
> 2.5V. The user must ensure that the
control pins are in the correct logic state when V
DD
> 2.5V to prevent unintentional writes.
Write Pulse "Glitch" Protection
Noise pulses of less than 10 nS (typical) on #OE, #OE, or #WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of #OE = V
IL
, #CE = V
IH
, or #WE = V
IH
. To initiate a write cycle
#CE and #WE must be a logical zero while #OE is a logical one.
Power-up Write and Read Inhibit
Power-up of the device with #WE = #CE = VIL and #OE = V
IH
will not accept commands on the rising
edge of #WE. The internal state machine is automatically reset to the read mode on power-up.
-4-
W49F002U
Command Definitions
Device operations are selected by writing specific address and data sequences into the command
register. Writing incorrect address and data values or writing them in the improper sequence will reset
the device to the read mode. "Command Definitions" defines the valid register command sequences.
Moreover, both Reset/Read commands are functionally equivalent, resetting the device to the read
mode.
Read Command
The device will automatically power-up in the read state. In this case, a command sequence is not
required to read data. Standard microprocessor read cycles will retrieve array data. This default value
ensures that no spurious alteration of the memory content occurs during the power transition.
The device will automatically returns to read state after completing an Embedded Program or
Embedded Erase algorithm.
Refer to the AC Read Characteristics and Waveforms for the specific timing parameters.
Auto-select Command
Flash memories are intended for use in applications where the local CPU can alter memory contents.
As such, manufacture and device codes must be accessible while the device resides in the target
system. PROM programmers typically access the signature codes by raising A9 to a high voltage.
However, multiplexing high voltage onto the address lines is not generally a desirable system design
practice.
The device contains an auto-select command operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the auto-select command sequence into the
command register. Following the command write, a read cycle from address XX00H retrieves the
manufacture code of DAh. A read cycle from address XX01H returns the device code (W49F002U =
0Bh).
Byte Program Command
The device is programmed on a byte-by-byte basis. Programming is a four-bus-cycle operation. The
program command sequence is initiated by writing two "unlock" write cycles, followed by the program
set-up command. The program address and data are written next, which in turn initiate the Embedded
program algorithm. Addresses are latched on the falling edge of #CE or #WE, whichever happens later
and the data is latched on the rising edge of #CE or #WE, whichever happens first. The rising edge of
#CE or #WE (whichever happens first) begins programming using the Embedded Program Algorithm.
Upon executing the algorithm, the system is not required to provide further controls or timings. The
device will automatically provide adequate internally generated program pulses and verify the
programmed cell margin.
The automatic programming operation is completed when the data on DQ7 (also used as Data Polling)
is equivalent to the data written to this bit at which time the device returns to the read mode and
addresses are no longer latched (see "Hardware Sequence Flags"). Therefore, the device requires that
a valid address to the device be supplied by the system at this particular instance of time for Data
Polling operations. Data Polling must be performed at the memory location which is being
programmed.
-5-
Publication Release Date: February 21, 2002
Revision A6
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