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SCAS331 − DECEMBER 1992 − REVISED MARCH 1994
CDC339
CLOCK DRIVER
WITH 3 STATE OUTPUTS
D
Low Output Skew, Low Pulse Skew for
D
D
Clock-Distribution and Clock-Generation
Applications
TTL-Compatible Inputs and Outputs
Distributes One Clock Input to Eight
Outputs
− Four Same-Frequency Outputs
− Four Half-Frequency Outputs
Distributed V
CC
and Ground Pins Reduce
Switching Noise
High-Drive Outputs (− 48-mA I
OH
,
48-mA I
OL
)
State-of-the-Art EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
Package Options Include Plastic
Small-Outline (DW) and Shrink
Small-Outline (DB) Packages
DB OR DW PACKAGE
(TOP VIEW)
D
D
D
D
Y3
GND
Y4
V
CC
OE
CLR
V
CC
Q4
GND
Q3
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Y2
GND
Y1
V
CC
CLK
GND
V
CC
Q1
GND
Q2
description
The CDC339 is a high-performance, low-skew clock driver. It is specifically designed for applications requiring
synchronized output signals at both the primary clock frequency and one-half the primary clock frequency. The
four Y outputs switch in phase and at the same frequency as the clock (CLK) input. The four Q outputs switch
at one-half the frequency of CLK.
When the output-enable (OE) input is low and the clear (CLR) input is high, the Y outputs follow CLK and the
Q outputs toggle on low-to-high transitions of CLK. Taking CLR low asynchronously resets the Q outputs to the
low level. When OE is high, the outputs are in the high-impedance state.
The CDC339 is characterized for operation from − 40°C to 85°C.
FUNCTION TABLE
INPUTS
OE
H
L
L
L
L
CLR
X
L
L
H
H
CLK
X
L
H
L
↑
OUTPUTS
Y1−Y4
Z
L
H
L
H
Q1−Q4
Z
L
L
Q0†
Q0†
† The level of the Q outputs before the
indicated steady-state input conditions were
established.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
1994, Texas Instruments Incorporated
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
1
SCAS331 − DECEMBER 1992 − REVISED MARCH 1994
CDC339
CLOCK DRIVER
WITH 3 STATE OUTPUTS
logic symbol
†
OE
5
EN
logic diagram (positive logic)
OE
5
18
18
Y1
Y2
Y3
Y4
Q1
Q2
Q3
Q4
CLK
16
T
CLR
6
R
13
3
Y4
1
Y3
20
Y2
Y1
CLK
16
20
1
3
13
T
11
10
R
8
CLR
6
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
Q1
11
Q2
10
Q3
8
Q4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
‡
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the disabled or power-off state, V
O
. . . . . . . . . . . . . . . −0.5 V to 5.5 V
Current into any output in the low state, I
O
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
Input clamp current, I
IK
(V
I
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −18 mA
Output clamp current, I
OK
(V
O
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Maximum power dissipation at T
A
= 55°C (in still air) (see Note 2): DB package . . . . . . . . . . . . . . . . . . 0.6 W
DW package . . . . . . . . . . . . . . . . . 1.6 W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the
Package Thermal Considerations
application note in the 1994
ABT Advanced BiCMOS Technology
Data Book,
literature number SCBD002B.
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SCAS331 − DECEMBER 1992 − REVISED MARCH 1994
CDC339
CLOCK DRIVER
WITH 3 STATE OUTPUTS
recommended operating conditions (see Note 3)
MIN
VCC
VIH
VIL
VI
IOH
IOL
fclock
TA
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
High-level output current
Low-level output current
Input clock frequency
Operating free-air temperature
−40
0
4.75
2
0.8
VCC
−48
48
80
85
MAX
5.25
UNIT
V
V
V
V
mA
mA
MHz
°C
NOTE 3: Unused pins (input or I/O) must be held high or low.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
VOL
IIH
IIL
IOZ
IO‡
ICC
Ci
Co
VCC = 4.75 V,
VCC = 4.75 V,
VCC = 4.75 V,
VCC = 5.25 V,
VCC = 5.25 V,
VCC = 5.25 V,
VCC = 5.25 V,
VCC = 5.25 V,
VI = VCC or GND
VI = 2.5 V or 0.5 V
VO = 2.5 V or 0.5 V
TEST CONDITIONS
II = −18 mA
IOH = − 48 mA
IOL = 48 mA
VI = 2.7 V
VI = 0.5 V
VO = 2.7 V or 0.5 V
VO = 2.5 V
Outputs high
IO = 0,
Outputs low
Outputs disabled
3
8
−50
MIN
2
0.5
50
−50
±
50
−180
70
85
70
pF
pF
mA
TYP†
MAX
−1.2
UNIT
V
V
V
µA
µA
µA
mA
† All typical values are at VCC = 5 V, TA = 25°C.
‡ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
fclock
tw
tsu
Clock frequency
CLR low
Pulse duration
Setup time
Clock duty cycle
CLK low
CLK high
CLR inactive before CLK↑
4
4
4
2
40%
60%
ns
ns
MAX
80
UNIT
MHz
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
SCAS331 − DECEMBER 1992 − REVISED MARCH 1994
CDC339
CLOCK DRIVER
WITH 3 STATE OUTPUTS
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figures 1 and 2)12
PARAMETER
fmax
tPLH
tPHL
tPHL
tPZH
tPZL
tPHZ
tPLZ
tsk(o)
tr
tf
† All typical values are at VCC = 5 V, TA = 25°C.
FROM
(INPUT)
TO
(OUTPUT)
MIN
80
3
CLK
CLR
OE
OE
Any Y or Q
Any Q
Any Y or Q
Any Y or Q
Y↑
CLK↑
Q↑
Y↑ and Q↑
0.9
0.7
3
4
2
3
2
2
9
9
9
7
7
7
7
0.75
0.9
0.9
ns
ns
ns
ns
ns
ns
ns
TYP†
MAX
UNIT
MHz
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
Embedded System
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