THIS DOCUMENT IS FOR MAINTENANCE
PURPOSES ONLY AND IS NOT
RECOMMENDED FOR NEW DESIGNS
FEBRUARY 1994
DS3002-2.0
VP101
30/50MHz 8-BIT CMOS VIDEO DAC
The VP101 is a CMOS 8-bit video DAC designed for
use in high performance, high resolution colour graphics
applications.
The device uses video control inputs (BLANK, SYNC
and REF WHITE) to provide the VP101 with the video
pedestal levels required to generate RS-343A compatible
video signals into a doubly-terminated 75
Ω
load, or
alternatively to produce RS-170 video signals across a
singly-terminated 75
Ω
load.
Data and control inputs are fully pipelined to maintain
synchronisation between the DAC outputs.
The full scale output current is defined by a 1.2V
reference and a single resistor. The reference voltage is
included on-chip in the VP101, but may be supplied
externally if required (see Fig. 2).
Differential and integral linearity errors of the D-A
converters are guaranteed to be a maximum of
±
1LSB over
the full operating temperature range.
G
4
R
7
R
6
R
5
R
4
B
7
B
6
B
5
B
4
V
AA
AGND
B
0
B
1
B
2
B
3
CLOCK
FEATURES
s
30/50MHz Pipeline Operation
s
Triple 8-Bit D-A Converters
s
±
1 LSB Differential Linearity Error
s
±
1 LSB Integral Linearity Error
s
Guaranteed Monotonic
s
RS-343A/RS-170 Compatible Levels
s
Drives Doubly Terminated 75
Ω
Load
s
Single 5V Power Supply
s
Typical Power Dissipation 500mW
s
Direct Replacement for Bt101
s
On-Chip Reference Available
APPLICATIONS
s
High Resolution Colour Graphics
s
CAE/CAD/CAM Applications
s
Image Processing
s
Video Reconstruction
s
Instrumentation
ORDERING INFORMATION
VP101-3 BA DP
(Commercial - Plastic DIL Package)
VP101-3 BA HP
(Commercial - J-lead Package)
VP101-5 BA DP
(Commercial - Plastic DIL Package)
VP101-5 BA HP
(Commercial - J-lead Package)
VP101-3 BA GP
(Commercial - Plastic Leaded Chip
Carrier, Gullwing formed leads)
R
0
R
1
R
2
R
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
G
5
G
6
G
7
BLANK
SYNC
AGND
IOB
IOR
IOG
I
SYNC
V
AA
AGND
FS ADJUST
V
REF
COMP
REF WHITE
G
3
G
2
G
1
G
0
DP40
V
REF
FS ADJUST
AGND
AGND
V
AA
V
AA
I
SYNC
IOG
IOR
IOB
AGND
17 COMP
16 REF WHITE
15 G
3
14 G
2
13 G
1
12 G
0
11 R
3
10 R
2
9 R
1
8 R
0
7
CLOCK
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
6 B
3
5 B
2
4 B
1
3 B
0
2 AGND
1 AGND
44 V
AA
43 V
AA
42 B
4
41 B
5
40 B
6
HP44
SYNC
BLANK
G
7
G
6
G
5
G
4
R
7
R
6
R
5
R
4
B
7
V
REF
FS ADJUST
AGND
AGND
V
AA
V
AA
I
SYNC
IOG
IOR
IOB
AGND
12
13
14
15
16
17
18
19
20
21
22
11 COMP
10 REF WHITE
9 G
3
8 G
2
7 G
1
6 G
0
5 R
3
4 R
2
3 R
1
2 R
0
1
CLOCK
44 B
3
43 B
2
42 B
1
41 B
0
40 AGND
39 AGND
38 V
AA
37 V
AA
36 B
4
35 B
5
34 B
6
ABSOLUTE MAXIMIM RATINGS
(Referenced to AGND)
DC supply voltage (V
AA
) -0.3 to +7V
Digital input voltage-0.3 to V
AA
+0.3V
Analog output short circuit duration Indefinite
Ambient operating temperature 0
°
C to +70
°
C
Storage temperature range-55
°
C to +125
°
C
GP44
SYNC
BLANK
G
7
G
6
G
5
G
4
R
7
R
6
R
5
R
4
B
7
23
24
25
26
27
28
29
30
31
32
33
Fig.1 Pin connections (not to scale) - top view
VP101
Fig.2 functional block diagram of VP101
RECOMENDED OPERATING CONDITIONS
Parameter
Supply voltage
Ambient operating temperature
Output load
Reference voltage
(internal or external)
FS ADJUST resistor
Symb
ol
V
AA
T
amb
R
L
V
REF
R
SET
1.14
Min.
4.75
0
37.5
1.20
542
1.26
Value
Typ.
5.00
Max.
5.25
+70
Units
V
°
C
Conditions
V
Ω
123
Ω
for RS-343A compatible output levels
THERMAL CHARACTERISTICS
DP HP GP
Thermal resistance, chip-to-case
θ
jc
= 12 17 17
°
C/W
Thermal resistance, chip-to-ambient
θ
jc
= 45 50 50
°
C/W
2
VP101
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
As specified in recommended operating conditions.
DC CHARACTERISTICS
Parameter
Resolution (each DAC)
Accuracy (each DAC)
Integral linearity error
Differential linearity error
Grey scale error
Monotonicity
Digital inputs
Input high voltage
Input low voltage
Input high current
Input low current
Analog outputs
Grey scale current range
Output currents
White level relative to blank level
White level relative to black level
Black level relative to blank level
Blank level on IOR, IOB
Blank level on IOG
Sync level on IOG
LSB size
DAC to DAC matching
Output compliance
External V
REF
input current
Internal voltage reference
Internal V
REF
temperature coefficient
LSB
V
OC
I
REF
V
REF
-0.5
1.14
1.20
40
INL
DNL
Symbol
Min.
8
±0.3
±0.3
±1%
guaranteed
3.0
AGND-0.3
±1
±1
±5%
Value
Typ.
Max.
Units
Bits
LSB
LSB
% grey scale
Conditions
V
IH
V
IL
I
IH
I
IL
V
AA
+0.3
1.2
+1
-1
20
255
19.06
276
17.62
255
1.44
21
5
0
7.62
111
5
69.1
2
+1.4
10
1.26
20.40
18.50
1.90
50
8.96
50
V
V
µA
µA
mA
LSB
mA
LSB
mA
LSB
mA
LSB
mA
LSB
mA
LSB
µA
LSB
µA
%
V
µA
V
ppm/°C
123
144424443
ns
ns
ns
ns
ns
binary
coding
15
17.69
16.74
0.95
0
6.29
0
RS-343A
tolerances
assumed
AC CHARACTERISTICS
Parameter
Max clock rate
Data and control setup time
Data and control hold time
Clock cycle time
Clock pulse width high time
Clock pulse width low time
Analog output delay
Analog output rise/fall time
Analog output settling time
Glitch energy
Analog output skew
Pipeline delay
V
AA
supply current
I
AA
Symbol
f
max
t
SU
t
H
t
CYC
t
CLKH
t
CLKL
t
DLY
t
VRF
t
S
Min.
50
6
2
20
8
8
10
8
12
100
0
1
1
120
3
1
175
1
15
100
0
1
100
VP101-5
Typ.
Max.
Min.
30
8
2
33.3
10
10
10
9
3
1
140
VP101-3
Typ.
Max.
Units
MHz
Conditions
ns
ns
ns
pV-sec
ns
Clock
mA
at f
max
, V
AA
= 5V
3
VP101
CIRCUIT DESCRIPTION
As shown in the Fig. 2, the VP101 contains three 8-bit
D-A converters, input latches, and a loop amplifier.
On the rising edge of each clock cycle, (see Fig. 4), 24
bits of colour information (R
0
-R
7
, G
0
-G
7
, and B
0
-B
7
) are
latched into the device and presented to the three 8-bit D-A
converters. The REF WHITE input, also latched on the rising
edge of each clock cycle, and will force the inputs of each D-
A converter to $FF.
SYNC and BLANK are latched on the rising edge of the
clock to maintain synchronisation with the colour data. These
inputs add appropriately weighted currents to the analog
outputs, producing the specific output levels required for
video applications as shown in Fig. 3. Table 1 details how the
SYNC, BLANK, and REFWHITE inputs modify the output
levels.
The I
SYNC
current output is typically connected directly
to the IOG output and is used to encode sync information
onto the IOG output. If I
SYNC
is not connected to the IOG
output, sync information will not be encoded on the green
channel, and the IOR, IOG and IOB outputs will have the
same full scale output current.
Full Scale output current is set by an external resistor
(R
SET
) between the FS ADJUST pin and AGND. R
SET
has a
typical value of 542Ω for generation of RS-343A video into a
37.5Ω load. The VP101 may be used in applications where
an external 1.2V (typical) reference is provided, in which
case the external reference should be temperature
compensated and provide a low impedance output.
The D-A converters on the VP101 use a segmented
architecture in which bit currents are routed to either the
output or AGND by a sophisticated decoding scheme.This
architecture eliminates the need for precision component
ratios and greatly reduces the switching transients
associated with turning current sources on or off.
Monotonicity and low glitch energy are guaranteed by using
identical current sources and current steering their outputs.
An on-chip operational amplifier stabilises the full scale
output current against temperature and power supply
variations.
The analog outputs of the VP101 are capable of directly
driving a 37.5Ω load, such as a doubly terminated 75Ω co-
axial cable or interpolation filters.
Fig.3 Composite video output waveform
Description
White Level
White Level
Data
Data-Sync
Blank Level
Blank-Sync
Blank Level
Sync Level
IOG
(mA)
26.68
26.68
Data + 9.06
Data + 1.44
9.06
1.44
7.62
0
IOR/IOB
(mA)
19.06
19.06
Data + 1.44
Data + 1.44
1.44
1.44
0
0
REF
WHITE
1
0
0
0
0
0
X
X
SYNC
1
1
1
0
1
0
1
0
BLANK
1
1
1
1
1
1
0
0
DAC
I/P Data
$XX
$FF
Data
Data
$00
$00
$XX
$XX
NOTE: Typical with full scale IOG = 26.68mA, R
SET
= 542Ω, V
REF
= 1.2V, I
SYNC
connected to IOG
Table 1: Video output truth table
4
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