Preliminary
XRD98L23
8-Bit, High-speed Linear CIS/CCD Sensor
Signal Processor with Serial Control
June 2000-2
FEATURES
APPLICATIONS
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·
·
·
·
·
·
·
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8-Bit Resolution, No Missing Codes
One-channel 10MSPS Pixel Rate
Dual-channel 5MSPS Pixel Rate
Three-channel 3 MSPS Pixel Rate
6-bit Programmable Gain Amplifier
8-bit Programmable Offset Adjustment
CIS or CCD Compatibility
Internal Clamp for CIS or CCD AC Coupled
Configurations
3.3V Operation & I/O Compatibility
Serial Load Control Registers
Low Power CMOS: 200mW-typ
Low Cost 20-Lead Packages
USB Compliant
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Check Scanners
General Purpose CIS or CCD Imaging
Low Cost Data Acquisition
Simple and Direct Interface to Canon 600 DPI
Sensors
GENERAL DESCRIPTION
The XRD98L23 is a complete linear CIS or CCD sensor
signal processor on a single monolithic chip. The
XRD98L23 includes a high speed 8-bit resolution ADC,
a 6-bit Programmable Gain Amplifier with gain adjust-
ment of 1 to 10, and 8-bit programmable input referred
offset calibration range of 800mV.
In the CCD configuration the input signal is AC coupled
with an external capacitor. An internal clamp sets the
black level. In the CIS configuration, the clamp switch
can be disabled and the CIS output signal is DC
coupled from the CIS sensor to the XRD98L23. The
CIS signal is level shifted to VRB in order to use the full
range of the ADC. In the CIS configuration the input
can also be AC coupled similar to the CCD configura-
tion. This enables CIS signals with large black levels
to be internally clamped to a DC reference equal to the
black level. The DC reference is internally subtracted
from the input signal.
The CIS configuration can also be used in other
applications that do not require CDS function, such as
low cost data acquisition.
ORDERING INFORMATION
Package Type
20-Lead SOIC
20-Lead SSOP
Temperature Range
0°C to +70°C
0°C to +70°C
Part Number
XRD98L23ACD
XRD98L23ACU
Rev. P2.00
EXAR
Corporation, 48720 Kato Road, Fremont, CA 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
Preliminary
PIN CONFIGURATION
XRD98L23
DVDD
DB0
DB1
DB2
DB3
DB4
DB5/SCLK
DB6/SDATA
DB7/LD
1
2
3
4
5
20
19
18
17
16
AVDD
RED
GRN
BLU
VDCEXT
VREF+
AGND
SYNCH
CLAMP
ADCCLK
XRD98L23ACD
6
7
8
9
15
14
13
12
11
DGND
10
20-Lead SOIC
PIN DESCRIPTION
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Symbol
DVDD
DB0
DB1
DB2
DB3
DB4
DB5/SCLK
DB6/SDATA
DB7/LD
DGND
ADCCLK
CLAMP
SYNCH
AGND
VREF+
VDCEXT
BLU
GRN
RED
AVDD
Description
Digital VDD (for Output Drivers)
Data Output Bit 0
Data Output Bit 1
Data Output Bit 2
Data Output Bit 3
Data Output Bit 4
Data Output Bit 5 & Data Input SCLK
Data Output Bit 6 & Data Input SDATA
Data Output Bit 7 & LD
Digital Ground (for Output Drivers)
A/D Converter Clock
Clamp and Video Sample Clock
Start of New Line and Serial Data Input Control
Analog Ground
A/D Positive Reference for Decoupling Cap
External DC Reference
Blue Input
Green Input
Red Input
Analog Power Supply
Rev. P2.00
3
XRD98L23
Preliminary
ELECTRICAL CHARACTERISTICS
Test Conditions: AV
DD
=DV
DD
=3.3V, ADCCLK=10MHz, 50% Duty Cycle, T
A
=25°C unless otherwise specified.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
Power Supplies
AV
DD
DV
DD
I
DD
IDD
PD
RES
F
s
DNL
INL
MON
V
RT
V
RB
DV
REF
R
L
PGARES
PGAG
MIN
PGAG
MAX
PGAGD
V
BLACK
DACRES
OFF
MIN
OFF
MAX
OFF
MIN
OFF
MAX
OFF∆
Analog Power Supply
Digital I/O Power Supply
Supply Current
Power Down Power Supply Current
Resolution
Maximum Sampling Rate
Differential Non-Linearity
Integral Non-Linearity
Monotonicity
Top Reference Voltage
Bottom Reference Voltage
Differential Reference Voltage
(V
RT
- V
RB
)
Ladder Resistance
300
600
780
Ω
PGA & Offset DAC Specifications
PGA Resolution
Minimum Gain
Maximum Gain
Gain Adjustment Step Size
Black Level Input Range
Offset DAC Resolution
Minimum Offset Adjustment
Maximum Offset Adjustment
Minimum Offset Adjustment
Maximum Offset Adjustment
Offset Adjustment Step Size
-100
8
-180
+200
-350
+100
-120
+360
-240
+240
1.88
-80
+400
-100
+350
6
0.950
9.5
1.0
10.0
0.14
500
1.35
10.50
Bits
V/V
V/V
V/V
mV
Bits
mV
mV
mV
mV
mV
Mode 111, D5=0 (Note 1)
Mode 111, D5=0
Mode 111, D5=1 (Note 1)
Mode 111, D5=1
DC Configuration
0.18
2.1
8
12
±0.5
±1.0
Yes
2.2
AV
DD
/10
0.67AV
DD
2.6
V
V
V
3.0
3.0
25
3.3
3.3
40
3.6
3.6
50
50
V
V
mA
µA
Bits
MSPS
LSB
LSB
(Note 2)
DV
DD
< AV
DD
V
DD
=3.0V
V
DD
=3.0V
ADC Specifications
Note 1:
Note 2:
The additional ±100 mV of adjustment with respect to the black level input range is needed to compensate
for any additional offset introduced by the XRD98L23 Buffer/PGA internally.
It is not recommended to operate the part between 3.6V and 4.4V.
Rev. P2.00
4
Preliminary
XRD98L23
ELECTRICAL CHARACTERISTICS (CONT'D)
Test Conditions: AV
DD
=DV
DD
=3.3V, ADCCLK=10MHz, 50% Duty Cycle, T
A
=25°C unless otherwise specified.
Symbol
I
IL
CIN
VIN
PP
Parameter
Input Leakage Current
Input Capacitance
AC Input Voltage Range
Min.
Typ.
Max.
100
10
0
AV
DD
-1.4
Unit
nA
pF
V
Conditions
Buffer Specifications
AC Input Voltage Range
0
DV
REF
V
VIN
DC Input Voltage Range
-0.1
AV
DD
-1.4
V
DC Input Voltage Range
V
DCEXT
-0.1
V
DCEXT
+
DV
REF
V
CIS AC; INT V
DCREF
Config Reg
=> XXX010XX
Gain=1 (Note 1)
CCD AC; INT V
DCREF
Config Reg
=> XXX011XX
Gain=1 (Note 1)
CIS DC; INT V
DCREF
Config Reg
=> XXX000XX
Gain=1 (Note 2)
CIS DC; EXT V
DCREF
Config Reg
=> XXX100XX
Gain=1 (Note 3)
V
DCEXT
+DV
REF
< AV
DD
CIS DC; EXT V
DCREF
Config Reg
=> XXX100XX
V
DCEXT
External DC Reference
0.3
AV
DD
/2
V
VIN
BW
VIN
CT
V
CLAMP
R
INT
R
OFF
Input Bandwidth (Small Signal)
Channel to Channel Crosstalk
Clamp Voltage
2.1
Clamp Switch On Resistance
Clamp Switch Off Resistance
12
10
-60
AGND
V
RT
180
50
250
MHz
dB
mV
V
Ω
MΩ
CIS (AC) Config
CCD (AC) Config
Internal Clamp Specifications
Note 1:
VIN
PP
is the signal swing before the external capacitor tied to the MUX inputs.
Note 2:
The -0.1V minimum is specified in order to accommodate black level signals lower than the external DC
reference (clamp) voltage.
Note 3:
The V
DCEXT
-0.1V minimum is specified in order to accommodate black level signals lower than the external DC
reference voltage.
Rev. P2.00
5
Embedded System
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