P4C168/P4C168L , P4C169, P4C170
ULTRA HIGH SPEED 4K x 4
STATIC CMOS RAMS
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 12/15/20/25/35ns (Commercial)
– 20/25/35/45/55/70ns (P4C168 Military)
Low Power Operation (Commercial)
– 715 mW Active
– 193 mW Standby (TTL Input) P4C168
– 83 mW Standby (CMOS Input) P4C168
Single 5V±10% Power Supply
Fully TTL Compatible, Common I/O Ports
Three Options
– P4C168 Low Power Standby Mode
– P4C169 Fast Chip Select Control
– P4C170 Fast Chip Select, Output Enable
Controls
Standard Pinout (JEDEC Approved)
– P4C168: 20-pin DIP, SOJ, LCC, SOIC,
CERPACK, and Flat Pack
– P4C169: 20-pin DIP and SOIC
– P4C170: 22-pin DIP
DESCRIPTION
The P4C168, P4C169 and P4C170 are a family of
16,384-bit ultra high-speed static RAMs organized as
4K x 4. All three devices have common input/output
ports.The P4C168 enters the standby mode when the
chip enable (CE) control goes HIGH; with CMOS input
levels, power consumption is only 83mW in this mode.
Both the P4C169 and the P4C170 offer a fast chip select
access time that is only 67% of the address access time.
In addition, the P4C170 includes an output enable (OE)
control to eliminate data bus contention. The RAMs oper-
ate from a single 5V ± 10% tolerance power supply.
Access times as fast as 12 nanoseconds are available,
permitting greatly enhanced system operating speeds.
CMOS is used to reduce power consumption to a low
715 mW active, 193 mW standby.
The P4C168 and P4C169 are available in 20-pin (P4C170
in 22-pin) 300 mil DIP packages providing excellent
board level densities. The P4C168 is also available in
20-pin 300 mil SOIC, SOJ, CERPACK, and Flat Pack
packages.
The P4C169 is also available in a 20-pin 300 mil SOIC
package.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
P4C168
P4C169
DIP (P2, C6, D2)
DIP (P2)
SOIC (S2)
SOIC (S2)
SOJ (J2)
CERPACK (F2)
SOLDER SEAL FLAT PACK (FS-2)
P4C170
DIP (P3)
Document #
SRAM107
REV E
1
Revised March 2010
P4C168/P4C168L, P4C169, P4C170
MAxIMUM RATINGS
(1)
Symbol Parameter
V
CC
V
TERM
T
A
Power Supply Pin with
Respect to GND
Terminal Voltage with
respect to GND (up to
7.0V)
Operating Temperature
Value
-0.5 to +7
-0.5 to V
CC
+ 0.5
-55 to +125
Unit
V
V
Symbol
T
BIAS
T
STG
P
T
°C
I
OUT
Parameter
Temperature Under
Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
-55 to +125
-65 to +150
1.0
50
Unit
°C
°C
W
mA
RECOMMENDED OPERATING CONDITIONS
Grade
(2)
Military
Ambient Temp
-55°C to +125°C
Gnd
0V
0V
Commercial 0°C to 70°C
V
CC
5.0V ± 10%
5.0V ± 10%
CAPACITANCES
(2)
Sym
C
IN
C
OUT
Parameter
(V
CC
= 5.0V, T
A
= 25°C, f = 1.0MHz)
Conditions Typ. Unit
V
IN
=0V
5
7
pF
pF
Input Capacitance
Output Capacitance V
OUT
=0V
DC ELECTRICAL CHARACTERISTICS
Sym Parameter
V
IH
V
IL
V
OL
V
OH
I
LI
I
LO
Input High Voltage
Input Low Voltage
Output Low Voltage (TTL Load)
Output High Voltage (TTL Load)
Input Leakage Current (Military)
Input Leakage Current (Commercial)
Output Leakage Current (Military)
Output Leakage Current (Commer-
cial)
I
CC
Dynamic Operating Current (Military)
Dynamic Operating Current (Com-
mercial)
I
SB
Standby Power Supply Current (TTL
Input Levels) (Military)
Standby Power Supply Current (TTL
Input Levels) (Commercial)
I
SB1
Standby Power Supply Current
(CMOS Input Levels) (Military)
Standby Power Supply Current
(CMOS Input Levels) (Commercial)
V
CC
=Max,f=Max, Outputs Open
I
OL
=+8 mA, V
CC
=Min
I
OH
=-4 mA, V
CC
=Min
V
CC
=Max, V
IN
=GND to V
CC
V
CC
=Max,
CS=V
IH
, V
OUT
=GND to
V
CC
2.4
-10
-5
-10
-5
—
—
—
—
—
—
+10
+5
+10
+5
120
100
40
35
20
15
Test Conditions
P4C168/169/170
Min
2.2
-0.5
(3)
P4C168L
Min
2.2
-0.5
(3)
Max
V
CC
+0.5
0.8
0.4
Max
V
CC
+0.5
0.8
0.4
Unit
V
V
V
V
2.4
-5
-2
-5
-2
—
—
—
—
—
—
+5
+2
+5
+2
120
100
40
µA
µA
mA
CE
1
≥V
IH
,V
CC
=Max,f=Max,Outputs
Open
mA
35
1
mA
0.2
CE
1
≥V
HC
,V
CC
=Max,f=0,Outputs
Open,V
IN
≤V
LC
or V
IN
≥V
HC
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
periods may affect reliability..
cause permanent damage to the device. This is a stress rating only 2. This parameter is sampled and not 100% tested.
and functional operation of the device at these or any other conditions 3. Transient inputs with V
IL
and I
IL
not more negative than -3.0V and -100mA,
above those indicated in the operational sections of this specification
respectively, are permissible for pulse widths up to 20 ns.
is not implied. Exposure to MAXIMUM rating conditions for extended
Document #
SRAM107
REV E
Page 2 of 14
P4C168/P4C168L, P4C169, P4C170
DATA RETENTION CHARACTERISTICS (P4C168L ONLY)
Sym
V
DR
I
CCDR
t
CDR
t
R†
Parameter
V
CC
for Data Retention
Data Retention Current (Military)
Data Retention Current (Commercial)
Chip Deselect to Data Retention Time
Operation Recovery Time
CE
≥ V
CC
- 0.2V,
V
IN
≥ V
CC
- 0.2V,
or V
IN
≤ 0.2V
Test Condition
Min
2.0
2
0.5
0
t
RC§
3
1.0
200
20
300
30
Typ. *
V
CC
=
2.0V
3.0V
Max
V
CC
=
2.0V
3.0V
Unit
V
µA
µA
ns
ns
DATA RETENTION WAVEFORM
AC CHARACTERISTICS—READ CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(4)
Sym Parameter
-12
Min
12
12
12
8
2
2
7
8
0
6
0
0
0
12
0
0
0
15
0
7
0
0
0
20
2
2
8
10
0
9
0
0
0
25
Max
Min
15
15
15
9
2
2
9
12
0
11
0
0
0
35
-15
Max
Min
20
20
20
12
2
2
10
15
0
15
-20
Max
Min
25
25
25
15
2
2
15
15
-25
Max
Min
35
35
35
20
-35
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
RC
t
AA
t
AC§
t
AC‡
t
OH
t
LZ‡
t
HZ†
t
OE†
Read Cycle Time
Address Access Time
Chip Enable Access Time
Chip Select Access Time
Output Hold from Address Change
Chip Enable to Output in Low Z
Chip Disable to Output in High Z
Output Enable to Data Valid
t
OLZ†
Output Enable to Output in Low Z
t
OHZ†
Output Disable to Output in High Z
t
RCS
t
RCH
t
PU§
t
PD§
Read Command Setup Time
Read Command Hold Time
Chip Enable to Power Up Time
Chip Disable to Power Down Time
Notes:
4. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
Document #
SRAM107
REV E
Page 3 of 14
P4C168/P4C168L, P4C169, P4C170
AC CHARACTERISTICS—READ CYCLE (CONTINUED)
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Sym Parameter
-45
Min
45
45
45
25
2
2
25
20
0
20
0
0
0
45
0
0
0
55
0
25
0
0
0
70
2
2
25
25
0
30
Max
Min
55
55
55
30
2
2
30
30
-55
Max
Min
70
70
70
35
-70
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
RC
t
AA
t
AC§
t
AC‡
t
OH
t
LZ‡
t
HZ†
t
OE†
Read Cycle Time
Address Access Time
Chip Enable Access Time
Chip Select Access Time
Output Hold from Address Change
Chip Enable to Output in Low Z
Chip Disable to Output in High Z
Output Enable to Data Valid
t
OLZ†
Output Enable to Output in Low Z
t
OHZ†
Output Disable to Output in High Z
t
RCS
t
RCH
t
PU§
t
PD§
Read Command Setup Time
Read Command Hold Time
Chip Enable to Power Up Time
Chip Disable to Power Down Time
§ P4C168 only
† P4C170 only
‡ Chip Select/Deselect for P4C169 and P4C170
TIMING WAVEFORM OF READ CYCLE NO. 1 (ADDRESS CONTROLLED)
(5,6)
Notes:
5.
WE
is HIGH for READ cycle.
6.
CE/CS
and
OE
are LOW for READ cycle.
Document #
SRAM107
REV E
Page 4 of 14
P4C168/P4C168L, P4C169, P4C170
TIMING WAVEFORM OF READ CYCLE NO. 2 (CE/CS CONTROLLED)
(5,7)
TIMING WAVEFORM OF READ CYCLE NO. 3—P4C170 ONLY (OE CONTROLLED)
(5)
Notes:
7. ADDRESS must be valid prior to, or coincident with
CE/CS
transition
low. For Fast
CS,
t
AA
must still be met.
8. Transition is measured ±200mV from steady state voltage prior to
change, with loading as specified in Figure 1.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
Document #
SRAM107
REV E
Page 5 of 14
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