PDM34078
3.3V 32K x 32 Fast CMOS
Synchronous Static RAM
with Burst Counter
and Output Register
Features
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Description
The PDM34078 is a 1,048,576 bit synchronous
random access memory organized as 32,768 x 32
bits. This device designed with burst mode
capability and interface controls to provide high-
performance in second level cache designs for x86,
Pentium, 680x0, and PowerPC microprocessors.
Addresses, write data and all control signals except
output enable are controlled through positive edge-
triggered registers. Write cycles are self-timed and
are also initiated by the rising edge of the clock.
Controls are provided to allow burst reads and
writes of up to four words in length. A 2-bit burst
address counter controls the two least-significant
bits of the address during burst reads and writes.
The burst address counter selectively uses the 2-bit
counting scheme required by the x86 and Pentium
or 680x0 and PowerPC microprocessors as con-
trolled by the mode pin. Individual write strobes
provide byte write for the four 8-bit bytes of data.
An asynchronous output enable simplifies interface
to high-speed buses.
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Interfaces directly with the x86, Pentium™, 680X0
and PowerPC™ processors
(100, 80, 66, 60, 50 MHz)
Single 3.3V power supply
Mode selectable for interleaved or linear burst:
Interleaved for x86 and Pentium
Linear for 680x0 and PowerPC
High-speed clock cycle times:
10, 12.5, 15, 16.7 and 20 ns
High-density 32K x 32 architecture with burst
address counter and output register
Fully registered inputs and outputs for pipelined
operation
High-output drive: 30 pF at rated T
A
Asynchronous output enable
Self-timed write cycle
Separate byte write enables and one global write
enable
Internal burst read/write address counter
Internal registers for address, data, controls
Output data register
Burst mode selectable
Sleep mode
Packages:
100-pin QFP - (Q)
100-pin TQFP - (TQ)
TM
i486, Pentium are trademarks of Intel Corp. PowerPC is a trademark of the International Business Machines Corporation.
1
Rev 1.0 - 5/01/98
PDM34078
Pinout
Name
A14-A2
A1, A0
DQ1-DQ32
NC
MODE
(1)
ADV
ADSC
ADSP
GW
FT
(1)
I/O
I
I
I/O
—
I
I
I
I
I
I
Description
Address Inputs A14-A2
Address Inputs A1 & A0
Read/Write Data
No Connect
Burst Sequence Select
Burst Counter Advance
Controller Address Status
Processor Address Status
Global Write
Must be tied HIGH for
proper operation
Name
CE
, CE2,
CE2
BWE
BW1
-
BW4
OE
I/O
I
I
I
I
I
I
—
—
—
—
Description
Chip Enables
Byte Write Enable
Byte Write Enables
Output Enable
Clock
Sleep Mode
Power Supply (+3.3V)
Output Power for DQ’s (+3.3V
±5%)
Array Ground
Output Ground for DQ’s
CLK
ZZ
V
CC
V
CCQ
V
SS
V
SSQ
NOTE: 1.MODE and
FT
are DC operated pins. Do not alter input state while device is operating.
Burst Sequence Table
Burst Sequence
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
Note:
Interleaved
(1)
Mode = NC or
V
CC
A14-A2, A1, A0
A14-A2, A1, A0
A14-A2, A1, A0
A14-A2, A1, A0
A14-A2,0,0
A14-A2,0,1
A14-A2,1,0
A14-A2,1,1
Linear
(2)
Mode = V
SS
A14-A2,0,1
A14-A2,1,0
A14-A2,1,1
A14-A2,0,0
A14-A2,1,0
A14-A2,1,1
A14-A2,0,0
A14-A2,0,1
A14-A2,1,1
A14-A2,0,0
A14-A2,0,1
A14-A2,1,0
1. Interleaved = x86 and Pentium.
2. Linear = 680x0 and Power PC compatible.
Asynchronous Truth Table
Operation
Partial Truth Table for Writes
GW
BWE
BW1 BW2 BW3 BW4
Function
ZZ
OE
I/O Status
Read
Read
Write
Deselected
Sleep
L
L
L
L
H
L
H
X
X
X
Data Out
High-Z
High-Z: Write Data In
High-Z
High-Z
H
H
H
H
L
H
L
L
L
X
X
H
L
L
X
X
H
H
L
X
X
H
H
L
X
X
H
H
L
X
READ
READ
WRITE Byte 1
WRITE All Bytes
WRITE All Bytes
NOTE: 1. L = Low, H = High, X = Don’t Care.
2. For a write operation following a read operation,
OE must be high before the input data required
setup time and held high through the input data
hold time.
3. This device contains circuitry that will ensure
the outputs will be in high-Z during powerup.
NOTE: 1. L = Low, H = High, X = Don’t Care.
2. Using BWE and BW1 through BW4, any one or
more bytes may be written.
4
Rev 1.0 - 5/01/98
PDM34078
Synchronous Truth Table
(See Notes 1 through 3)
CE
H
L
L
L
L
L
L
X
H
X
H
L
X
H
X
H
CE2
X
X
H
X
H
L
L
X
X
X
X
L
X
X
X
X
CE2
X
L
X
L
X
H
H
X
X
X
X
H
X
X
X
X
ADSP
X
L
L
H
H
L
H
H
X
H
X
H
H
X
H
H
ADSC
L
X
X
L
L
X
L
H
H
H
H
L
H
H
H
H
ADV
X
X
X
X
X
X
X
L
L
H
H
X
L
L
H
H
BWx
X
X
X
X
X
X
X
H
H
H
H
L
L
L
L
L
CLK
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
Address
N/A
N/A
N/A
N/A
N/A
External
External
Next
Next
Current
Current
External
Next
Next
Current
Current
Operation
Deselected
Deselected
Deselected
Deselected
Deselected
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Begin Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
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NOTES:
1. X = Don’t Care, H = logic High, L = logic Low, BWx = any one or more byte write enable signals (BW1, BW2, BW3, BW4)
and BWE are low, or GW is low.
2. BW1 enables BWx to Byte 1 (DQ1-DQ8). BW2 enables BWx to Byte 2 (DQ9-DQ16).
BW3 enables BWx to Byte 3 (DQ17-DQ24), BW4 enables BWx to Byte 4 (DQ25-DQ32).
3. ADV must always be high at the rising edge of the first clock after an ADSP cycle is initiated if a write cycle is desired (to
ensure use of correct address).
Rev 1.0 - 5/01/98
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FPGA/CPLD
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