K7N803645M
K7N801845M
Document Title
256Kx36 & 512Kx18 Pipelined NtRAM
TM
256Kx36 & 512Kx18-Bit Pipelined NtRAM
TM
Revision History
Rev. No.
0.0
0.1
History
1. Initial document.
1. Changed speed bin from 167MHz to 150MHz
2. Changed DC Parameters;
I
CC
: from 400mA to 450mA , ISB : from 60mA to 20mA
I
SB2
: from 50mA to 85mA
1. Changed speed bin from 150MHz to 167MHz
2. Changed Power from 3.3V to 2.5V
3. Changed N.C pins to Power and ZZ Pin #14, #16, #64, #66
4. Changed some control pin names.
from CEN to CKE, from BWEx to BWx
5. Modify absolute maximum ratings
V
DD
; from 4.0V to 3.6V, V
IN
; from 4.6V to 3.6V
6. Changed DC parameters
I
SB
; from 20mA to 80mA, I
SB2
; from 85mA to 10mA
V
OL
; from 0.4V to 0.2V, V
OH
; from 2.4V to 2.0V
V
IL
; from 0.8V to 0.7V, V
IH
; from 2.0V to 1.7V
7. A
DD
the sleep mode timing and characteristics
CKE controlled timing and CS controlled timing
1. Removed speed bin 167MHz
2.Changed AC parameters
t
HZOE
; from 4.0 to 3.5 , t
HZC
;from 4.0 to 3.5 at -75
t
HZOE
; from 5.0 to 3.5 , t
HZC
;from 5.0 to 3.5 , t
CL/H
; 4.0 to 3.0 at -10
3.Modify Sleep Mode Waveform.
Changed Sleep Mode Electrical Characteristics .
t
PDS
;from Max 2cycle to Min 2cycle
t
PUS
; from Max 2cycle to Min 2cycle
1.Modify from ADV to ADV at timing.
2.A
DD
the Trade Mark( NtRAM
TM
)
1. Changed DC parameters
I
SB1
; from 10mA to 20mA, I
SB2
; from 10mA to 20mA
1. Changed t
CD
,t
OE
from 4.0ns to 4.2ns at -75.
1. Changed DC condition at Icc and parameters
I
CC
; from 420mA to 320mA at -67 , from 370mA to 300mA at -75
from 300mA to 250mA at -10.
I
SB
; from 70mA to 60mA at -67 , from 60mA to 50mA at -75
from 50mA to 40mA at -10.
1.Changed V
OL
Max value from 0.2V to 0.4V .
1. Add 119BGA(7x17 Ball Grid Array Package) .
1. Final spec release
1. Add t
CYC
167Mhz.
Draft Date
September. 1997
November. 1997
Remark
Preliminary
Preliminary
0.2
March. 11. 1998
Preliminary
0.3
April. 11. 1998
Preliminary
0.4
June. 02. 1998
Preliminary
0.5
Aug. 19. 1998
Preliminary
0.6
0.7
Sep. 28. 1998
Nov. 10. 1998
Preliminary
Preliminary
0.8
0.9
1.0
2.0
Dec. 23. 1998
Mar. 03. 1999
April. 01. 1999
Oct. 30. 1999
Preliminary
Preliminary
Final
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
November 1999
Rev 3.0
K7N803645M
K7N801845M
Document Title
256Kx36 & 512Kx18 Pipelined NtRAM
TM
256Kx36 & 512Kx18-Bit Pipelined NtRAM
TM
Revision History
Rev. No.
3.0
History
1. Remove 119BGA package .
Draft Date
Nov. 19. 1999
Remark
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-2-
November 1999
Rev 3.0
K7N803645M
K7N801845M
256Kx36 & 512Kx18 Pipelined NtRAM
TM
256Kx36 & 512Kx18-Bit Pipelined NtRAM
TM
FEATURES
• 2.5V
±5%
Power Supply.
• Byte Writable Function.
• Enable clock and suspend operation.
• Single READ/WRITE control pin.
• Self-Timed Write Cycle.
• Three Chip Enable for simple depth expansion with no data
contention .
•
Α
interleaved burst or a linear burst mode.
• Asynchronous output enable control.
• Power Down mode.
• TTL-Level Three-State Outputs.
•100-TQFP-1420A .
GENERAL DESCRIPTION
The K7N803645M and K7N801845M are 9,437,184 bits Syn-
chronous Static SRAMs.
The NtRAM
TM
, or No Turnaround Random Access Memory uti-
lizes all the bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-chip
write pulse generation
and provides increased timing flexibility for incoming signals.
For read cycles, pipelined SRAM output data is temporarily
stored by an edge triggered output register and then released
to the output buffers at the next rising edge of clock.
The K7N803645M and K7N801845M are implemented with
SAMSUNG′s high performance CMOS technology and is avail-
able in 100pin TQFP packages. Multiple power and ground pins
minimize ground bounce.
FAST ACCESS TIMES
PARAMETER
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol -16 -15 -13 -10 Unit
t
CYC
t
CD
t
OE
6.0 6.7 7.5
10
ns
ns
ns
3.5 3.8 4.2 5.0
3.5 3.8 4.2 5.0
LOGIC BLOCK DIAGRAM
LBO
A [0:17]or
A [0:18]
ADDRESS
REGISTER
A
2
~A
17
or A
2
~A
18
A
0
~A
1
BURST
ADDRESS
COUNTER
A′
0
~A′
1
256Kx36 , 512Kx18
MEMORY
ARRAY
CLK
CKE
K
WRITE
ADDRESS
REGISTER
WRITE
ADDRESS
REGISTER
CONTROL
LOGIC
K
DATA-IN
REGISTER
DATA-IN
REGISTER
K
CS
1
CS
2
CS
2
ADV
WE
BW
x
(x=a,b,c,d or a,b)
OE
ZZ
DQa
0
~ DQd
7
or DQa
0
~ DQb
8
DQPa ~ DQPd
36 or 18
CONTROL
REGISTER
CONTROL
LOGIC
K
OUTPUT
REGISTER
BUFFER
NtRAM
TM
and No Turnaround Random Access Memory are trademarks of Samsung,
and its architecture and functionalities are supported by NEC and Toshiba.
-3-
November 1999
Rev 3.0
K7N803645M
K7N801845M
PIN CONFIGURATION
(TOP VIEW)
BWd
BWb
256Kx36 & 512Kx18 Pipelined NtRAM
TM
BWa
BWc
CKE
ADV
N.C.
CLK
CS
1
CS
2
CS
2
V
DD
V
SS
WE
A
17
83
OE
A
6
A
7
A
8
82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
81
A
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
N.C.
N.C.
N.C.
N.C.
V
DD
A
5
A
4
A
3
A
2
A
1
A
0
A
10
A
11
A
12
A
13
A
14
A
15
PIN NAME
SYMBOL
A
0
- A
17
PIN NAME
Address Inputs
TQFP PIN NO.
32,33,34,35,36,37,
44,45,46,47,48,49,
50,81,82,83,99,100
85
88
89
87
98
97
92
93,94,95,96
86
64
31
SYMBOL
V
DD
V
SS
N.C.
DQa
0
~a
7
DQb
0
~b
7
DQc
0
~c
7
DQd
0
~d
7
DQPa~P
d
V
DDQ
V
SSQ
PIN NAME
Power Supply(+2.5V)
Ground
No Connect
Data Inputs/Outputs
TQFP PIN NO.
14,15,16,41,65,66,91
17,40,67,90
38,39,42,43,84
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
ADV
WE
CLK
CKE
CS
1
CS
2
CS
2
BWx
OE
ZZ
LBO
Address Advance/Load
Read/Write Control Input
Clock
Clock Enable
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Power Sleep Mode
Burst Mode Control
LBO
V
SS
Output Power Supply
(+2.5V)
Output Ground
Notes :
1. The pin 84 is reserved for address bit for the 16Mb NtRAM.
2. A
0
and A
1
are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
-4-
A
16
50
DQPc
DQc
0
DQc
1
V
DDQ
V
SSQ
DQc
2
DQc
3
DQc
4
DQc
5
V
SSQ
V
DDQ
DQc
6
DQc
7
V
DD
V
DD
V
DD
V
SS
DQd
0
DQd
1
V
DDQ
V
SSQ
DQd
2
DQd
3
DQd
4
DQd
5
V
SSQ
V
DDQ
DQd
6
DQd
7
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
K7N803645M(256Kx36)
DQPb
DQb
7
DQb
6
V
DDQ
V
SSQ
DQb
5
DQb
4
DQb
3
DQb
2
V
SSQ
V
DDQ
DQb
1
DQb
0
V
SS
V
DD
V
DD
ZZ
DQa
7
DQa
6
V
DDQ
V
SSQ
DQa
5
DQa
4
DQa
3
DQa
2
V
SSQ
V
DDQ
DQa
1
DQa
0
DQPa
November 1999
Rev 3.0
K7N803645M
K7N801845M
PIN CONFIGURATION
(TOP VIEW)
BWb
256Kx36 & 512Kx18 Pipelined NtRAM
TM
BWa
CKE
ADV
CS
2
N.C.
N.C.
N.C.
CLK
CS
1
CS
2
V
DD
V
SS
WE
A
18
83
OE
A
6
A
7
A
8
82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
81
A
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
N.C.
N.C.
N.C.
N.C.
V
DD
A
5
A
4
A
3
A
2
A
1
A
0
A
11
A
12
A
13
A
14
A
15
A
16
PIN NAME
SYMBOL
A
0
- A
18
PIN NAME
Address Inputs
TQFP PIN NO.
32,33,34,35,36,37,
44,45,46,47,48,49,50,
80,81,82,83,99,100
85
88
89
87
98
97
92
93,94
86
64
31
SYMBOL
V
DD
V
SS
N.C.
PIN NAME
Power Supply(+2.5V)
Ground
No Connect
TQFP PIN NO.
14,15,16,41,65,66,91
17,40,67,90
1,2,3,6,7,25,28,29,30,
38,39,42,43,51,52,53,
56,57,75,78,79,84,95,96
58,59,62,63,68,69,72,73,74
8,9,12,13,18,19,22,23,24
ADV
WE
CLK
CKE
CS
1
CS
2
CS
2
BWx
OE
ZZ
LBO
Address Advance/Load
Read/Write Control Input
Clock
Clock Enable
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Power Sleep Mode
Burst Mode Control
LBO
V
SS
DQa
0
~a
8
DQb
0
~b
8
Data Inputs/Outputs
V
DDQ
V
SSQ
Output Power Supply
(+2.5V)
Output Ground
A
17
50
N.C.
N.C.
N.C.
V
DDQ
V
SSQ
N.C.
N.C.
DQb
8
DQb
7
V
SSQ
V
DDQ
DQb
6
DQb
5
V
DD
V
DD
V
DD
V
SS
DQb
4
DQb
3
V
DDQ
V
SSQ
DQb
2
DQb
1
DQb
0
N.C.
V
SSQ
V
DDQ
N.C.
N.C.
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
K7N801845M(512Kx18)
A
10
N.C.
N.C.
V
DDQ
V
SSQ
N.C.
DQa
0
DQa
1
DQa
2
V
SSQ
V
DDQ
DQa
3
DQa
4
V
SS
V
DD
V
DD
ZZ
DQa
5
DQa
6
V
DDQ
V
SSQ
DQa
7
DQa
8
N.C.
N.C.
V
SSQ
V
DDQ
N.C.
N.C.
N.C.
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
Notes :
1. The pin 84 is reserved for address bit for the 16Mb NtRAM.
2. A
0
and A
1
are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
-5-
November 1999
Rev 3.0
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