Datasheet
RMQCBA3636DGBA, RMQCBA3618DGBA
36-Mbit DDR™ II+ SRAM 2-word Burst
Architecture (2.5 Cycle Read latency)
Description
The RMQCBA3636DGBA is a 1,048,576-word by 36-bit and the RMQCBA3618DGBA is a 2,097,152-word by 18-bit
synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor
memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers are
controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products are
suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit
configuration. These products are packaged in 165-pin plastic FBGA package.
R10DS0244EJ0100
Rev. 1.00
Jul. 15, 2015
Features
Power Supply
1.8 V for core (V
DD
), 1.4 V to V
DD
for I/O (V
DDQ
)
Clock
Fast clock cycle time for high bandwidth
Two input clocks (K and /K) for precise DDR timing at clock rising edges only
Two output echo clocks (CQ and /CQ) simplify data capture in high-speed systems
Clock-stop capability with
µs
restart
I/O
Common data input/output bus
Pipelined double data rate operation
HSTL I/O
User programmable output impedance
PLL circuitry for wide output data valid window and future frequency scaling
Data valid pin (QVLD) to indicate valid data on the output
Function
Two-tick burst for low DDR transaction size
Internally self-timed write control
Simple control logic for easy depth expansion
JTAG 1149.1 compatible test access port
Package
165 FBGA package (13 x 15 x 1.4 mm)
R10DS0244EJ0100 Rev. 1.00
Jul. 15, 2015
Page 1 of 29
RMQCBA3636DGBA, RMQCBA3618DGBA
Datasheet
Orderable Part Name Definition
Column
No.
Example
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
R
M
Q
X
X
A
X
X
X
X
D
G
B
A
-
1
8
2
#
A
C
0
RM QCB A 36 36 D G BA－18 2 # A C 0
Renesas Internal use
Pb-Free
Tray
Industrial Temp.
Cycle Time
( T
A
= -40℃ to 85℃ )
Package Type
Quality Level
Internal Code
I/O Bus Width
Memory Size
1.8V V
DD
QDR SRAM / DDR SRAM
Renesas Memory
R10DS0244EJ0100 Rev. 1.00
Jul. 15, 2015
Page 2 of 29
RMQCBA3636DGBA, RMQCBA3618DGBA
Datasheet
Pin Arrangement
[RMQCBA3636DGBA]
1M x 36
(Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
/CQ
NC
NC
NC
NC
NC
NC
/DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC
DQ27
NC
DQ29
NC
DQ30
DQ31
V
REF
NC
NC
DQ33
NC
DQ35
NC
TCK
3
SA
DQ18
DQ28
DQ19
DQ20
DQ21
DQ22
V
DDQ
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
SA
4
R-/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
/BW2
/BW3
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
/K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
QVLD
NC
7
/BW1
/BW0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
/LD
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
NC
NC
DQ17
NC
DQ15
NC
NC
V
REF
DQ13
DQ12
NC
DQ11
NC
DQ9
TMS
11
CQ
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
Notes: 1.
2.
Address expansion order for future higher density SRAMs: 9A
→
3A
→
10A
→
2A
→
7A
→
5B.
NC pins can be left floating or connected to 0V to V
DDQ
R10DS0244EJ0100 Rev. 1.00
Jul. 15, 2015
Page 4 of 29
RMQCBA3636DGBA, RMQCBA3618DGBA
[RMQCBA3618DGBA]
2M x 18
(Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
/CQ
NC
NC
NC
NC
NC
NC
/DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC
DQ9
NC
NC
NC
DQ12
NC
V
REF
NC
NC
DQ15
NC
NC
NC
TCK
3
SA
NC
NC
DQ10
DQ11
NC
DQ13
V
DDQ
NC
DQ14
NC
NC
DQ16
DQ17
SA
4
R-/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
/BW1
NC
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
/K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
QVLD
NC
7
NC
/BW0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
/LD
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
SA
NC
DQ7
NC
NC
NC
NC
V
REF
DQ4
NC
NC
DQ1
NC
NC
TMS
Datasheet
11
CQ
DQ8
NC
NC
DQ6
DQ5
NC
ZQ
NC
DQ3
DQ2
NC
NC
DQ0
TDI
Notes: 1.
2.
Address expansion order for future higher density SRAMs: 9A
→
3A
→
10A
→
2A
→
7A
→
5B.
NC pins can be left floating or connected to 0V to V
DDQ
R10DS0244EJ0100 Rev. 1.00
Jul. 15, 2015
Page 5 of 29
ADI Reference Circuit
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