PACVGA200
VGA Port Companion Circuit
Product Description
The PACVGA200 incorporates seven channels of ESD protection
for all signal lines commonly found in a VGA port. ESD protection is
implemented with current steering diodes designed to safely handle
the high surge currents encountered with IEC−61000−4−2 Level−4
ESD Protection (8 kV contact discharge). When a channel is
subjected to an electrostatic discharge, the ESD current pulse is
diverted via the protection diodes into either the positive supply rail or
ground where it may be safely dissipated. Separate positive supply
rails are provided for the VIDEO, DDC and SYNC channels to
facilitate interfacing with low voltage Video Controller ICs and
provide design flexibility in multi−supply−voltage environments.
Two non−inverting drivers provide buffering for the HSYNC and
VSYNC signals from the Video Controller IC (SYNC_IN1,
SYNC_IN2). These buffers accept TTL input levels and convert them
to CMOS output levels that swing between Ground and V
CC
4.
These drivers have nominal 60
W
output impedance (R
S
) to match
the characteristic impedance of the HSYNC & VSYNC lines of the
video cables typically used in PC applications. Two N−channel FETs
provide the level shifting function required when the DDC controller
is operated at a lower supply voltage than the monitor. Three 75
W
termination resistors suitable for terminating the video signals from
the video DAC are also provided. These resistors have separate input
pins to allow insertion of additional EMI filtering, if required, between
the termination point and the ESD protection diodes. These resistors
are matched to better than 2% for excellent signal level matching for
the R/G/B signals.
When the PWR_UP input is driven LOW, the SYNC inputs can be
floated without causing the SYNC buffers to draw any current from
the V
CC
4 supply. When the PWR_UP input is LOW, the SYNC
outputs are driven LOW.
An internal diode (D1 in schematic on previous page) is also
provided so that V
CC
3 can be derived from V
CC
4, if desired, by
connecting V
CC
3 to V_BIAS. In applications where V
CC
4 may be
powered down, diode D1 blocks any DC current paths from the
DDC_OUT pins back to the powered down V
CC
4 rail via the top ESD
protection diodes.
Features
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QSOP24
QR SUFFIX
CASE 492B
MARKING DIAGRAM
PACVGA200QR
AWLYWW
PACVGA200QR = Specific Device Code
A
= Assembly Location
WL
= Wafer Lot
Y
= Year
WW
= Work Week
ORDERING INFORMATION
Device
PACVGA200QR
Package
QSOP24
(Pb−Free)
Shipping
†
2500/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Single Chip Solution for the VGA Port Interface
Includes ESD Protection, Level Shifting, and RGB
75
W
Termination Resistors for VIDEO Lines
Termination
Seven Channels of ESD Protection for All VGA Port
Connector Pins Meeting IEC−61000−4−2 Level−4 ESD
Requirements (8 kV Contact Discharge)
Very Low Loading Capacitance from ESD Protection
Diodes on VIDEO Lines, 4 pF Typical
Applications
(Matched to 1% Typ.)
TTL to CMOS Level−Translating Buffers with Power
Down Mode for HSYNC and VSYNC Lines
Bi−Directional Level Shifting N−Channel FETs
Provided for DDC_CLK & DDC_DATA Channels
Compact 24−Pin QSOP Package
These Devices are Pb−Free and are RoHS Compliant
Notebook Computers with VGA Port
Semiconductor Components Industries, LLC, 2011
Desktop PCs with VGA Port
1
Publication Order Number:
PACVGA200/D
October, 2011
−
Rev. 3
PACVGA200
SIMPLIFIED ELECTRICAL SCHEMATIC
V
CC
1
2
GNDD
VIDEO_1
VIDEO_2
VIDEO_3
3
4
5
DDC_IN1
R
C
16
15
DDC_OUT1
R
B
GNDD
GNDD
6
V
CC
2
GNDD
TERM_1
TERM_2
TERM_3
GNDA
8
9
10
7
GNDA
75
75
75
GNDD
GNDD
GNDD
GNDD
DDC_IN2
17
R
C
18
GNDD
V
CC
3
GNDD
DDC_OUT2
SYNC_IN2
21
V
CC
4
1
GNDD
GNDD 11
PWR_UP
SYNC_IN1
19
23
SD1
V
CC
2 V 3
CC
12
14
V_BIAS
13
V
CC
4
1
R
S
20
D1
SYNC_OUT1
R
C
GNDD
R
S
22
SYNC_OUT2
24
SD2
GNDD
PACKAGE / PINOUT DIAGRAMS
Top View
V
CC
4
V
CC
1
VIDEO_1
VIDEO_2
VIDEO_3
GNDD
GNDA
TERM_1
TERM_2
TERM_3
PWR_UP
V
CC
2
1
2
3
4
5
6
7
8
9
10
11
12
24−Pin QSOP
24
23
22
21
20
19
18
17
16
15
14
13
SD2
SD1
SYNC_OUT2
SYNC_IN2
SYNC_OUT1
SYNC_IN1
DDC_OUT2
DDC_IN2
DDC_IN1
DDC_OUT1
V
CC
3
V_BIAS
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PACVGA200
Table 1. PIN DESCRIPTIONS
Lead(s)
1
2
3−5
6
7
8−10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Name
V
CC
4
V
CC
1
VIDEO_1, VIDEO_2, VIDEO_3
GNDD
GNDA
TERM_1, TERM_2, TERM_3
PWR_UP
V
CC
2
V_BIAS
V
CC
3
DDC_OUT1
DDC_IN1
DDC_IN2
DDC_OUT2
SYNC_IN1
SYNC_OUT1
SYNC_IN2
SYNC_OUT2
SD1
SD2
Description
Positive voltage supply pin. This is an isolated V
CC
pin for the SYNC_1, SYNC_2, SD1
and SD2 circuits.
Positive voltage supply pin. This is an isolated V
CC
pin for the VIDEO_1, VIDEO_2
and VIDEO_3 ESD circuits.
RGB Video Protection Channels. These pins tie to the RGB video lines (for example,
the Blue signal) between the VGA controller device and the video connector.
Digital Ground reference supply pin.
Ground reference supply pin for TERM_1, TERM_2 and TERM_3 pins.
RGB Video Termination Channels. These pins tie to the RGB video lines (for example,
the Blue signal) providing a 75
W
termination to GNDA for the given video channel.
Sync Signal Output 1. Ties to the video connector side of one of the sync lines
(for example the Horizontal Sync signal).
Positive voltage supply pin. This is an isolated V
CC
pin for the DDC_IN1 and DDC_IN2
input circuits. Defines the logic one level for the DDC_OUTn outputs.
Used to derive V
CC3
from V
CC4
input.
Positive voltage supply pin. This is an isolated V
CC
pin for the DDC_OUT1
and DDC_OUT2 ESD protection circuits.
DDC Signal Output 1. Connects to the connector side of one of the DDC signals
(for example, the bidirectional DDC_Data serial line).
DDC Signal Input 1. Connects to the VGA Controller side of one of the DDC signals
(for example, the bidirectional DDC_Data serial line).
DDC Signal Input 2. Connects to the VGA Controller side of one of the DDC signals
(for example, the bidirectional DDC_Clk).
DDC Signal Output 2. Connects to the connector side of one of the DDC signals
(for example, the bidirectional DDC_Clk).
Sync Signal Buffer Input 1. Connects to the VGA Controller side of one of the sync lines
(for example, the Horizontal Sync signal).
Sync Signal Buffer Output 1. Connects to the video connector side of one of the sync lines
(for example the Horizontal Sync signal).
Sync Signal Buffer Input 2. Connects to the VGA Controller side of one of the sync lines
(for example, the Vertical Sync signal).
Sync Signal Buffer Output 2. Connects to the video connector side of one of the sync lines
(for example the Vertical Sync signal).
Sync Signal Filter 1. Connects to the video connector side of one of the sync lines
(for example the Vertical Sync signal).
Sync Signal Filter 2. Connects to the video connector side of one of the sync lines
(for example the Horizontal Sync signal).
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PACVGA200
SPECIFICATIONS
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
V
CC
1, V
CC
2, V
CC
3 and V
CC
4 Supply Voltage
Diode D1 Forward DC Current
Storage Temperature Range
DC Voltage at Inputs
VIDEO_1, VIDEO_2, VIDEO_3
TERM_1, TERM_2, TERM_3
DDC_IN1, DDC_IN2
DDC_OUT1, DDC_OUT2
SYNC_IN1, SYNC_IN2
Package Power Rating
Rating
[GND
−
0.5] to +6.0
100
−65
to +150
[GND
−
0.5] to [V
CC
1 + 0.5]
−6.0,
+6.0
[GND
−
0.5] to [V
CC
2 + 0.5]
[GND
−
0.5] to [V
CC
3 + 0.5]
[GND
−
0.5] to [V
CC
4 + 0.5]
1000
Units
V
mA
C
V
mW
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. STANDARD OPERATING CONDITIONS
Parameter
Operating Temperature Range
Rating
0 to +70
Units
C
Table 4. ELECTRICAL OPERATING CHARACTERISTICS
(Note 1)
Symbol
I
CC1
I
CC2
,
I
CC3
I
CC4
Parameter
V
CC
1 Supply Current
V
CC
2 & V
CC
3 Supply Current
V
CC
4 Supply Current
Conditions
V
CC
1 = 5.0 V, VIDEO inputs at V
CC
1
or GND level
V
CC
2 = V
CC
3 = 5.0 V
V
CC
4 = 5.0 V, SYNC Inputs at GND or
V
CC
4 Level, PWR−UP pin at V
CC
4,
SYNC Outputs Unloaded
V
CC
4 = 5.0 V, SYNC Inputs at 3.0 V,
PWR−UP Pin at V
CC
4, SYNC Outputs
Unloaded
V
CC
4 = 5.0 V, PWR−UP Input at GND,
SYNC Outputs Unloaded
V
BIAS
R
T
V
IH
V
IL
V
OH
V
OL
R
OH
R
OL
R
B
, R
P
R
C
I
N
Resistor Value
V
CC
2 Pull−down Resistor Value
Input Current
VIDEO Inputs
HSYNC, VSYNC Inputs
PWR_UP = V
CC
3 = 5.0 V
V
CC
2 = 3.0 V
V
CC
1= 5.0 V, V
IN
= V
CC
1 or GND
V
CC
4 = 5.0 V, V
IN
= V
CC
4 or GND
V
BIAS
Open Circuit Voltage
Video Termination Resistance
R
T
Resistance Matching
Logic High Input Voltage
Logic Low Input Voltage
Logic High Output Voltage
Logic Low Output Voltage
Output Resistance
V
CC
4 = 5.0 V (Note 2)
V
CC
4 = 5.0 V (Note 2)
I
OH
=
−4
mA, V
CC
4 = 5.0 V (Note 2)
I
OL
= 4 mA, V
CC
4 = 5.0 V (Note 2)
(Note 2)
4.5
0.18
50
45
0.5
0.5
1.0
1.5
2.0
0.8
4.8
0.32
125
80
2.0
3.0
1
1
No External Current Drawn from
V
BIAS
Pin
71.25
V
CC
4−0.8
75
1
78.75
2
10
Min
Typ
Max
10
10
Units
mA
mA
mA
200
mA
10
mA
V
W
%
V
V
V
V
W
W
MW
MW
mA
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PACVGA200
Table 4. ELECTRICAL OPERATING CHARACTERISTICS
(Note 1)
Symbol
I
OFF
Parameter
Off−State Leakage Current,
Level−Shifting NFET
V
ON
C
IN
Voltage Drop Across Level
Shifting NFET when Turned ON
Input Capacitance
VIDEO_1,VIDEO_2 & VIDEO_3
Inputs
Conditions
(V
CC
2
−
V
DDC_IN
)
0.4 V,
V
DDC_OUT
= V
CC
2
(V
CC
2
−
V
DDC_OUT
)
0.4 V,
V
DDC_IN
= V
CC
2
V
CC
2 = 2.5 V, V
S
= GND, I
DS
= 3 mA
Min
Typ
Max
10
10
0.15
V
pF
Units
mA
V
CC
1 = 5.0 V, V
IN
= 2.5 V,
Measured at 1 MHz
V
CC
1 = 2.5 V, V
IN
= 1.25 V,
Measured at 1 MHz
C
L
= 50 pF, V
CC
= 5.0 V,
Input t
R
and t
F
5 ns
C
L
= 50 pF, V
CC
= 5.0 V,
Input t
R
and t
F
5 ns
C
L
= 50 pF, V
CC
= 5.0 V,
Input t
R
and t
F
5 ns
(Measured 10%
−
90%)
V
CC
1 = V
CC
3 = V
CC
4 = 5 V (Note 3)
3.0
3.0
4.0
4.5
8.0
8.0
5.0
5.6
12.0
12.0
10.0
t
PLH
t
PHL
t
R,
t
F
SYNC Drivers L
H Propagation
Delay
SYNC Drivers H
L Propagation
Delay
SYNC Drivers Output Rise & Fall
Times
ESD Withstand Voltage
ns
ns
ns
5.0
7.0
V
ESD
8
kV
1. All parameters specified over standard operating conditions unless otherwise noted.
2. This parameter applies only to the HSYNC and VSYNC channels. HSYNC and VSYNC have 8 mA drivers with R
S
added in series to
terminate transmission line.
3. Per the IEC−61000−4−2 International ESD Standard, Level 4 contact discharge method. V
CC
1, V
CC
3 and V
CC
4 must be bypassed to GND
via a low impedance ground plane with a 0.2
mF,
low inductance, chip ceramic capacitor at each supply pin. ESD pulse is applied between
the applicable pins and GND. ESD pulse can be positive or negative with respect to GND. Applicable pins are: VIDEO_1, VIDEO_2,
VIDEO_3, SYNC_OUT1, SD1, SYNC_OUT2, SD2, DDC_OUT1 and DDC_OUT2. All other pins are ESD protected to the industry standard
2 kV per the Human Body Model (MIL−STD−883, Method 3015).
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