DPE128X32V-12I datasheet, PDF - EEWORLD Datasheet

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DPE128X32V-12I: DescriptionEEPROM Module, 512KX8, 120ns, Parallel, CMOS, CPGA66, PGA-66; Categorystorage storage; File Size586KB，6 Pages; ManufacturerB&B Electronics Manufacturing Company

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DPE128X32V-12I Overview

EEPROM Module, 512KX8, 120ns, Parallel, CMOS, CPGA66, PGA-66

DPE128X32V-12I Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	PGA
package instruction	PGA, PGA66,11X11
Contacts	66
Reach Compliance Code	unknown
ECCN code	3A991.B.1.B.1
Maximum access time	120 ns
Other features	CONFIGURABLE AS 128K X 32
Spare memory width	16
Data polling	YES
JESD-30 code	S-CPGA-P66
JESD-609 code	e0
length	27.686 mm
memory density	4194304 bit
Memory IC Type	EEPROM MODULE
memory width	8
Number of functions	1
Number of terminals	66
word count	524288 words
character code	512000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	512KX8
Output characteristics	3-STATE
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Encapsulate equivalent code	PGA66,11X11
Package shape	SQUARE
Package form	GRID ARRAY
page size	128 words
Parallel/Serial	PARALLEL
power supply	5 V
Programming voltage	5 V
Certification status	Not Qualified
Maximum seat height	7.62 mm
Maximum standby current	0.0012 A
Maximum slew rate	0.32 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
switch bit	NO
width	27.686 mm
Maximum write cycle time (tWC)	10 ms
Base Number Matches	1

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4 Megabit CMOS EEPROM

DPE128X32V

DESCRIPTION:

The DPE128X32V is a high-performance Electrically Erasable

and Programmable Read Only Memory (EEPROM) module

and may be organized as 128K X 32, 256K X 16 or 512K X 8.

The module is built with four low-power CMOS 128K X 8

EEPROMs. The four chip enables are used for individual

BWDW* selection. The DPE128X32V is ideally suited for

those computer systems having 16-bit or 32-bit architectures.

The DPE128X32V contains a 128-BWDW page register to

allow writing of up to 128 BWDWs simultaneously. During

a write cycle, the address and 1 to 128 BWDWs of data are

internally latched, freeing the address and data bus for other

operations. Following the initiation of a write cycle, the

module will automatically write the latched data using an

internal control timer. The end of a write cycle can be

detected by DATA Polling of the most significant data bit in

each byte. Once the end of a write cycle has been detected,

a new access for a read or write can begin.

FUNCTIONAL BLOCK DIAGRAM

FEATURES:

•

Fast Access Times: 120, 150, 200, 250ns

Organizations Available:

128K X 32, 256K X 16 or 512K X 8

Automatic Page Write Operation

Internal Address and Data Latches

Internal Control Timer

Fast Write Cycle Times

Page Write Cycle Time: 10ms maximum

1 to 128 BWDW* Page Write Operation

DATA Polling for END of Write Detection

High Reliability CMOS Technology

Endurance: 10

Cycles

Data Retention: 10 years

Single +5V Power Supply,

±10%

Tolerance

CMOS and TTL Compatible Inputs and Outputs

Available with All Semiconductor Components

used to Construct the Module Compliant to

MIL-STD-883; Class B

66-Pin PGA (Grid Array) Package

Same Package as other Versapac Versions

(SRAMs, EPROMs, and Mixed)

PIN NAMES

A0 - A16

I/O0 - I/O31

CE0 - CE3

WE0 - WE3

N.C.

Address Inputs

Data In/Out

Chip Enables

Write Enables

Output Enable

Power (+5V)

Ground

No Connect

* Byte, Word or Double Word (BWDW).

PIN-OUT DIAGRAM

30A014-25

REV. D

This document contains information on a product that is currently released

to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the

right to change products or specifications herein without prior notice.

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