®
ISO
2
-CMOS
MT8960/61/62/63/64/65/66/67
Integrated PCM Filter Codec
Features
•
•
•
•
•
•
ST-BUS™ compatible
Transmit/Receive filters & PCM Codec in one
I.C
Meets AT&T D3/D4 and CCITT G711 and G712
µ-Law:
MT8960/62/64/67
A-Law: MT8961/63/65/67
Low power consumption:
Op.: 30 mW typ.
Stby.: 2.5 mW typ.
Digital Coding Options:
MT8964/65/66/67 CCITT Code
MT8960/61/62/63 Alternative Code
Digitally controlled gain adjust of both filters
Analog and digital loopback
Filters and codec independently user
accessible for testing
Powerdown mode available
2.048 MHz master clock input
Up to six uncommitted control outputs
±5V
±5% power supply
ISSUE 10
May 1995
Ordering Information
MT8964/65AC
18 Pin Ceramic DIP
MT8960/61/64/65AE
18 Pin Plastic DIP
MT8962/63AE
20 Pin Plastic DIP
MT8962/63/66/67AS
20 Pin SOIC
0°C to+70°C
Description
Manufactured in ISO
2
-CMOS, these integrated filter/
codecs are designed to meet the demanding
performance needs of the digital telecommunications
industry, e.g., PABX, Central Office, Digital
telephones.
•
•
•
•
•
•
•
•
ANUL
V
X
Transmit
Filter
Analog to
Digital PCM
Encoder
Output
Register
DSTo
SD0
SD1
SD2
SD3
SD4
SD5
B-Register
8-Bits
Output
Register
A Register
8-Bits
CSTi
CA
Control
Logic
F1i
C2i
V
R
Receive
Filter
PCM Digital
to Analog
Decoder
Input
Register
DSTi
V
Ref
GNDA
GNDD
V
DD
V
EE
Figure 1 - Functional Block Diagram
6-19
MT8960/61/62/63/64/65/66/67
ISO
2
-CMOS
MT8960/61/64/65
CSTi
DSTi
C2i
DSTo
VDD
F1i
CA
SD3
SD2
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
GNDD
VRef
GNDA
VR
ANUL
VX
VEE
SD0
SD1
CSTi
DSTi
C2i
DSTo
VDD
SD5
SD4
F1i
CA
SD3
MT8962/63/66/67
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GNDD
VRef
GNDA
VR
ANUL
VX
VEE
SD0
SD1
SD2
18 PIN CERDIP/PDIP
20 PIN PDIP/SOIC
Figure 2 - Pin Connections
Pin Description
Pin Name
CSTi
Description
Control ST-BUS In
is a TTL-compatible digital input used to control the function of the filter/codec.
Three modes of operation may be effected by applying to this input a logic high (V
DD
), logic low
(GNDD), or an 8-bit serial word, depending on the logic states of CA and F1i.
Functions controlled are: powerdown, filter gain adjust, loopback, chip testing, SD outputs.
Data ST-BUS In
accepts the incoming 8-bit PCM word. Input is TTL-compatible.
Clock Input
is a TTL-compatible 2.048 MHz clock.
Data ST-BUS Out
is a three-state digital output driving the PCM bus with the outgoing 8-bit PCM
word.
Positive power Supply
(+5V).
Synchronization Input
is an active low digital input enabling (in conjunction with CA) the PCM input,
PCM output and digital control input. It is internally sampled on every positive edge of the clock, C2i,
and provides frame and channel synchronization.
Control Address
is a three-level digital input which enables PCM input and output and determines
into which control register (A or B) the serial data, presented to CSTi, is stored.
System Drive Output
is an open drain output of an N-channel transistor which has its source tied to
GNDA. Inactive state is open circuit.
System Drive Outputs
are open drain outputs of N-channel transistors which have their source tied
to GNDD. Inactive state is open circuit.
System Drive Outputs
are “Totempole“ CMOS outputs switching between GNDD and V
DD
. Inactive
state is logic low.
Negative power supply
(-5V).
Voice Transmit
is the analog input to the transmit filter.
Auto Null
is used to integrate an internal auto-null signal. A 0.1µF capacitor must be connected
between this pin and GNDA.
Voice Receive
is the analog output of the receive filter.
Analog ground
(0V).
Voltage Reference
input to D to A converter.
Digital ground
(0V).
DSTi
C2i
DSTo
V
DD
F1i
CA
SD3
SD4-5
SD0-2
V
EE
V
X
ANUL
V
R
GNDA
V
Ref
GNDD
6-20
ISO
2
-CMOS
MT8960/61/62/63/64/65/66/67
MT8960/62
Digital Output
11111111
11110000
11100000
11010000
11000000
10110000
10100000
10010000
10000000
00000000
00010000
00100000
00110000
01000000
01010000
01100000
01110000
01111111
-2.415V
Bit 7...
MSB
0
LSB
-1.207V
0V
+1.207V +2.415V
Analog Input Voltage (V
IN
)
MT8964/66
Digital Output
10000000
10001111
10011111
10101111
10111111
11001111
11011111
11101111
11111111
01111111
01101111
01011111
01001111
00111111
00101111
00011111
00001111
00000000
Figure 3 -
µ-Law
Encoder Transfer Characteristic
MT8961/63
Digital Output
11111111
11110000
11100000
11010000
11000000
10110000
10100000
10010000
10000000
00000000
00010000
00100000
00110000
01000000
01010000
01100000
01110000
01111111
-2.5V
Bit 7...
MSB
0
LSB
-1.25V
0V
+1.25V
+2.5V
Analog Input Voltage (V
IN
)
MT8965/67
Digital Output
10101010
10100101
10110101
10000101
10010101
11100101
11110101
11000101
11010101
01010101
01000101
01110101
01100101
00010101
00000101
00110101
00100101
00101010
Figure 4 - A-Law Encoder Transfer Characteristic
6-21
MT8960/61/62/63/64/65/66/67
Functional Description
Figure 1 shows the functional block diagram of the
MT8960-67. These devices provide the conversion
interface between the voiceband analog signals of a
telephone subscriber loop and the digital signals
required in a digital PCM (pulse code modulation)
switching system. Analog (voiceband) signals in the
transmit path enter the chip at V
X
, are sampled at
8kHz, and the samples quantized and assigned 8-bit
digital values defined by logarithmic PCM encoding
laws. Analog signals in the receive path leave the
chip at V
R
after reconstruction from digital 8-bit
words.
Separate switched capacitor filter sections are used
for bandlimiting prior to digital encoding in the
transmit path and after digital decoding in the receive
path. All filter clocks are derived from the 2.048 MHz
master clock input, C2i. Chip size is minimized by
the use of common circuitry performing the A to D
and D to A conversion. A successive approximation
technique is used with capacitor arrays to define the
16 steps and 8 chords in the signal conversion
process. Eight-bit PCM encoded digital data enters
and leaves the chip serially on DSTi and DSTo pins,
respectively.
ISO
2
-CMOS
are 30 dB for 0-60 Hz and 35 dB for 4.6 kHz and
above.
The filter output signal is an 8 kHz staircase
waveform which is fed into the codec capacitor array,
or alternatively, into an external capacitive load of
250 pF when the chip is in the test mode. The digital
encoder generates an eight-bit digital word
representation of the 8 kHz sampled analog signal.
The first bit of serial data stream is bit 7 (MSB) and
represents the sign of the analog signal. Bits 4-6
represent the chord which contains the analog
sample value. Bits 0-3 represent the step value of
the analog sample within the selected chord. The
MT8960-63 provide a sign plus magnitude PCM
output code format. The MT8964/66 PCM output
code conforms to the AT &T D3 specification, i.e.,
true sign bit and inverted magnitude bits. The
MT8965/67 PCM output code conforms to the CCITT
specifications with alternate digit inversion (even bits
inverted). See Figs. 3 and 4 for the digital output
code corresponding to the analog voltage, V
IN
, at V
X
input.
The eight-bit digital word is output at DSTo at a
nominal rate of 2.048 MHz, via the output buffer as
the first 8-bits of the 125 µs sampling frame.
Transmit Path
Analog signals at the input (Vx) are firstly
bandlimited to 508 kHz by an RC lowpass filter
section. This performs the necessary anti-aliasing
for the following first-order sampled data lowpass
pre-filter which is clocked at 512 kHz. This further
bandlimits the signal to 124 kHz before a fifth-order
elliptic lowpass filter, clocked at 128 kHz, provides
the 3.4 kHz bandwidth required by the encoder
section. A 50/60 Hz third-order highpass notch filter
clocked at 8 kHz completes the transmit filter path.
Accumulated DC offset is cancelled in this last
section by a switched-capacitor auto-zero loop which
integrates the sign bit of the encoded PCM word, fed
back from the codec and injects this voltage level
into the non-inverting input of the comparator. An
integrating capacitor (of value between 0.1 and 1 µF)
must be externally connected from this point (ANUL)
to the Analog Ground (GNDA).
The absolute gain of the transmit filter (nominally 0
dB at 1 kHz) can be adjusted from 0 dB to 7 dB in 1
dB steps by means of three binary controlled gain
pads.
The resulting bandpass characteristics with the limits
shown in Figure 10 meet the CCITT and AT&T
recommended specifications. Typical atttenuations
6-22
Receive Path
An eight-bit PCM encoded digital word is received on
DSTi input once during the 125 µs period and is
loaded into the input register. A charge proportional
to the received PCM word appears on the capacitor
array and an 8 kHz sample and hold circuit
integrates this charge and holds it for the rest of the
sampling period.
The receive (D/A) filter provides interpolation filtering
on the 8 kHz sample and hold signal from the codec.
The filter consists of a 3.4 kHz lowpass fifth-order
elliptic section clocked at 128 kHz and performs
bandlimiting and smoothing of the 8 kHz "staircase"
waveform. In addition, sinx/x gain correction is
applied to the signal to compensate for the
attenuation of higher frequencies caused by the
capacitive sample and hold circuit. The absolute
gain of the receive filter can be adjusted from 0 dB to
-7 dB in 1 dB steps by means of three binary
controlled gain pads.
The resulting lowpass
characteristics, with the limits shown in Figure 11,
meet the CCITT and AT & T recommended
specifications.
Typical attenuation at 4.6 kHz and above is 30 dB.
The filter is followed by a buffer amplifier which
will drive 5V peak/peak into a 10k ohm load, suitable
for driving electronic 2-4 wire circuits.
ISO
2
-CMOS
V
Ref
An external voltage must be supplied to the V
Ref
pin
which provides the reference voltage for the digital
encoding and decoding of the analog signal. For
V
Ref
= 2.5V, the digital encode decision value for
overload (maximum analog signal detect level) is
equal to an analog input V
IN
= 2.415V (µ-Law
version) or 2.5V (A-Law version) and is equivalent to
a signal level of 3.17 dBm0 or 3.14 dBm0
respectively, at the codec.
The analog output voltage from the decoder at V
R
is
defined as:
µ-Law:
V
Ref
MT8960/61/62/63/64/65/66/67
driving a large number of codecs due to the high
Normal
input impedance of the V
Ref
input.
precautions should be taken in PCB layout design to
minimize noise coupling to this pin. A 0.1 µF
capacitor connected from V
Ref
to ground and located
as close as possible to the codec is recommended to
minimize noise entering through V
Ref
. This capacitor
should have good high frequency characteristics.
Timing
The codec operates in a synchronous manner (see
Figure 9a). The codec is activated on the first
positive edge of C2i after F1i has gone low. The
digital output at DSTo (which is a three-state output
driver) will then change from a high impedance state
to the sign bit of the encoded PCM word to be
output. This will remain valid until the next positive
edge, when the next most significant bit will be
output.
On the first negative clock edge (after F1i signal has
been internally synchronized and CA is at GNDD or
V
EE
) the logic signal present at DSTi will be clocked
into the input shift register as the sign bit of the
incoming PCM word.
The eight-bit word is thus input at DSTi on negative
edges of C2i and output at DSTo on positive edges
of C2i.
F1i must return to a high level after the eighth
clock pulse causing DSTo to enter high impedance
and preventing further input data to DSTi. F1i will
continue to be sampled on every positive edge of
C2i. (Note: F1i may subsequently be taken low
during the same sampling frame to enable entry of
serial data into CSTi. This occurs usually mid-frame,
in conjunction with CA=V
DD
, in order to enter an 8-bit
control word into Register B. In this case, PCM input
and output are inhibited by CA at V
DD
.)
X
[(
-0.5
128
) ( )(
16.5 + S
)]
33
+
±
V
2
C
128
±
V
OFFSET
A-Law:
V
Ref
X
+
[( )(
0.532 S
)]
2
C+1
128
OFFSET
C=0
V
Ref
X
[( )(
2
C
128
16.5 + S
32
)]
±
V
OFFSET
C≠0
where
C
= chord number (0-7)
S
= step number (0-15)
V
Ref
is a high impedance input with a varying
capacitive load of up to 40 pF.
The recommended reference voltage for the MT8960
series of codecs is 2.5V ±0.5%. The output voltage
from the reference source should have a maximum
temperature coefficient of 100 ppm/C°. This voltage
should have a total regulation tolerance of ±0.5%
both for changes in the input voltage and output
loading of the voltage reference source. A voltage
reference circuit capable of meeting these
specifications is shown in Figure 5. Analog Devices
’AD1403A voltage reference circuit is capable of
NC
8
NC
7
NC
6
NC
5
V
Ref
0.1
µF
MT8960-67
FILTER/CODEC
AD1403A
1
2
3
4
NC
+5V
2.5V
Figure 5 - Typical Voltage Reference Circuit
6-23
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