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MT48V16M16LFFG-8XT

Description
Synchronous DRAM, 16MX16, 7ns, CMOS, PBGA54, 8 X 14 MM, VFBGA-54
Categorystorage    storage   
File Size2MB,61 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Download Datasheet Parametric View All

MT48V16M16LFFG-8XT Overview

Synchronous DRAM, 16MX16, 7ns, CMOS, PBGA54, 8 X 14 MM, VFBGA-54

MT48V16M16LFFG-8XT Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Parts packaging codeBGA
package instructionVFBGA, BGA54,9X9,32
Contacts54
Reach Compliance Codenot_compliant
ECCN codeEAR99
access modeFOUR BANK PAGE BURST
Maximum access time7 ns
Other featuresAUTO/SELF REFRESH
Maximum clock frequency (fCLK)125 MHz
I/O typeCOMMON
interleaved burst length1,2,4,8
JESD-30 codeR-PBGA-B54
JESD-609 codee0
length14 mm
memory density268435456 bit
Memory IC TypeSYNCHRONOUS DRAM
memory width16
Number of functions1
Number of ports1
Number of terminals54
word count16777216 words
character code16000000
Operating modeSYNCHRONOUS
Maximum operating temperature75 °C
Minimum operating temperature-25 °C
organize16MX16
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeVFBGA
Encapsulate equivalent codeBGA54,9X9,32
Package shapeRECTANGULAR
Package formGRID ARRAY, VERY THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)235
power supply1.8/2.5,2.5 V
Certification statusNot Qualified
refresh cycle8192
Maximum seat height1 mm
self refreshYES
Continuous burst length1,2,4,8,FP
Maximum standby current0.0005 A
Maximum slew rate0.165 mA
Maximum supply voltage (Vsup)2.7 V
Minimum supply voltage (Vsup)2.3 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL EXTENDED
Terminal surfaceTin/Lead/Silver (Sn/Pb/Ag)
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature30
width8 mm
Base Number Matches1
PRELIMINARY
256Mb: x16
MOBILE SDRAM
MOBILE SDRAM
Features
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE and Auto Refresh Modes
• Self Refresh Mode
• 64ms, 8,192-cycle refresh
• LVTTL-compatible inputs and outputs
• Low voltage power supply
• Temperature Compensated Self Refresh (TCSR)
Option
Marking
V
DD
/V
DD
Q
LC
3.3V/3.3V
G
3.0V/3.0V
V
2.5V/2.5V-1.8V
• Configurations
16M16
16 Meg x 16 (4 Meg x 16 x 4 banks)
• Plastic Packages - OCPL
TG
54-pin TSOP (400 mil)
1
1
P
54-pin TSOP (400 mil) Lead-Free
2
FG
54-ball VFBGA (8mm x 14mm)
2
BG
54-ball VFBGA (8mm x 14mm) Lead-Free
2
F8
54-ball VFBGA (11mm x 8mm)
2
B8
54-ball VFBGA (11mm x 8mm) Lead-Free
• Timing (Cycle Time)
-75
7.5ns @ CL = 3 (133MHz)
-8
8.0ns @ CL = 3 (125 MHz)
-10
9.6ns @ CL = 3 (104 MHz)
• Self Refresh
None
Standard
• Operating Temperature
None
Commercial (0
o
C to + 70
o
C)
o
o
XT
Extended (-25 C to + 75 C)
o
C to + 85
o
C)
IT
Industrial (-40
NOTE:
1. Contact Factory for availability.
2. Due to space limitations, FBGA-packaged components have an
abbreviated part marking that is different from the part number.
For a quick conversion of an FBGA code, see the FBGA Part Marking
Decoder on the Micron web site,
www.micron.com/decoder.
MT48LC16M16LF, MT48G16M16LF,
MT48V16M16LF
4 MEG X 16 X 4 BANKS
Figure 1: Ball Assignment (Top View)
54-Ball VFBGA
1
A
B
C
D
E
F
G
H
J
V
SS
2
DQ15
DQ13
DQ11
DQ9
NC
CLK
A11
A7
A5
3
V
SS
Q
4
5
6
7
V
DD
Q
8
DQ0
9
V
DD
DQ14
V
DD
Q
V
SS
Q
DQ2
DQ1
DQ12
V
SS
Q
V
DD
Q
DQ4
DQ3
DQ10
V
DD
Q
V
SS
Q
DQ6
DQ5
DQ8
V
SS
V
DD
LDQM
DQ7
UDQM
CKE
CAS\
RAS\
WE\
A12
A9
BA0
BA1
CS\
A8
A6
A0
A1
A10
V
SS
A4
A3
A2
VDD
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
16 Meg x 16
4 Meg x 16 x 4 banks
8K
8K (A0-A12)
4 (BA0, BA1)
512 (A0-A8)
Table 1:
SPEED
GRADE
Key Timing Parameters
ACCESS TIME
1
CL=1
CL=2
CL=3
SETUP
TIME
HOLD
TIME
CLOCK
FREQUENCY
-75
-8
-10
-75
-8
-10
-8
NOTE:
133 MHz
125 MHz
104 MHz
104 MHz
104 MHz
83 MHz
50 MHz
-
-
-
-
-
-
19ns
-
-
8ns
6ns
8ns
8ns
-
5.4ns
7ns
7ns
-
-
-
-
1.5ns
2.5ns
2.5ns
1.5ns
2.5ns
2.5ns
2.5ns
0.8ns
1.0ns
1.0ns
1.0ns
1.0ns
1.0ns
1.0ns
1. *CL = CAS (READ) latency
09005aef80737ef7
256Mbx16_1.fm - Rev. E 4/04 EN
1
©2002 Micron Technology, Inc. All rights reserved.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.

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