DM74S74 Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear, and Complementary Outputs
August 1986
Revised April 2000
DM74S74
Dual Positive-Edge-Triggered D Flip-Flops
with Preset, Clear, and Complementary Outputs
General Description
This device contains two independent positive-edge-trig-
gered D flip-flops with complementary outputs. The infor-
mation on the D input is accepted by the flip-flops on the
positive going edge of the clock pulse. The triggering
occurs at a voltage level and is not directly related to the
transition time of the rising edge of the clock. The data on
the D input may be changed while the clock is LOW or
HIGH without affecting the outputs as long as setup and
hold times are not violated. A low logic level on the preset
or clear inputs will set or reset the outputs regardless of the
logic levels of the other inputs.
Ordering Code:
Order Number
DM74S74M
DM74S74N
Package Number
M14A
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Inputs
PR
L
H
L
H
H
H
CLR
H
L
L
H
H
H
CLK
X
X
X
↑
↑
L
D
X
X
X
H
L
X
Q
H
L
H*
H
L
Q
0
Outputs
Q
L
H
H*
L
H
Q
0
H
=
HIGH Logic Level
X
=
Either LOW or HIGH Logic Level
L
=
LOW Logic Level
↑ =
Positive-going Transition
*
=
This configuration is nonstable; that is, it will not persist when either the
preset and/or clear inputs return to its inactive (HIGH) level.
Q
0
=
The output logic level of Q before the indicated input conditions were
established.
© 2000 Fairchild Semiconductor Corporation
DS006457
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DM74S74
Absolute Maximum Ratings
(Note 1)
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
Storage Temperature Range
7V
5.5V
0°C to
+70°C
−65°C
to
+150°C
Note 1:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Recommended Operating Conditions
Symbol
V
CC
V
IH
V
IL
I
OH
I
OL
f
CLK
f
CLK
t
W
Supply Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Current
LOW Level Output Current
Clock Frequency (Note 2)
Clock Frequency (Note 3)
Pulse Width
(Note 2)
Clock HIGH
Clock LOW
Clear LOW
Preset LOW
t
W
Pulse Width
(Note 3)
Clock HIGH
Clock LOW
Clear LOW
Preset LOW
t
SU
t
SU
t
H
t
H
T
A
Setup Time (Note 2)(Note 4)
Setup Time (Note 3)(Note 4)
Input Hold Time (Note 2)(Note 4)
Input Hold Time (Note 3)(Note 4)
Free Air Operating Temperature
0
0
6
7.3
7
7
8
9
9
9
3↑
3↑
2↑
2↑
0
70
ns
ns
ns
ns
°C
ns
ns
110
95
Parameter
Min
4.75
2
0.8
−1
20
75
65
Nom
5
Max
5.25
Units
V
V
V
mA
mA
MHz
MHz
Note 2:
C
L
=
15 pF, R
L
=
280Ω, T
A
=
25°C and V
CC
=
5V.
Note 3:
C
L
=
50 pF, R
L
=
280Ω, T
A
=
25°C and V
CC
=
5V.
Note 4:
The symbol (↑) indicates the rising edge at the clock pulse is used for reference.
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2
DM74S74
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
V
I
V
OH
V
OL
I
I
I
IH
Parameter
Input Clamp Voltage
HIGH Level
Output Voltage
LOW Level
Output Voltage
HIGH Level
Input Current
Conditions
V
CC
=
Min, I
I
= −
18 mA
V
CC
=
Min, I
OH
=
Max
V
IL
=
Max, V
IH
=
Min
V
CC
=
Min, I
OL
=
Max
V
IH
=
Min, V
IL
=
Max
V
CC
=
Max
V
I
=
2.7V
D
Clear
Preset
Clock
I
IL
LOW Level
Input Current
V
CC
=
Max
V
I
=
0.5V
(Note 6)
I
OS
I
CC
Short Circuit Output Current
Supply Current
V
CC
=
Max (Note 7)
V
CC
=
Max, (Note 8)
D
Clear
Preset
Clock
−40
30
2.7
3.4
0.5
1
50
150
100
100
−2
−6
−4
−4
−100
50
mA
mA
mA
µA
Min
Typ
(Note 5)
Max
−1.2
Units
V
V
V
mA
Input Current @ Max Input Voltage V
CC
=
Max, V
I
=
5.5V
Note 5:
All typicals are at V
CC
=
5V, T
A
=
25°C.
Note 6:
Clear is tested with preset HIGH and preset is tested with clear HIGH.
Note 7:
Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 8:
With all outputs OPEN, I
CC
is measured with the Q and Q outputs HIGH in turn. At the time of measurement, the clock is grounded.
Switching Characteristics
at V
CC
=
5V and T
A
=
25°C
R
L
=
280Ω
Symbol
Parameter
From (Input)
To (Output)
f
MAX
t
PLH
t
PLH
t
PHL
Maximum Clock Frequency
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
(Clock HIGH)
t
PHL
Propagation Delay Time
HIGH-to-LOW Level Output
(Clock LOW)
t
PHL
Propagation Delay Time
HIGH-to-LOW Level Output
(Clock HIGH)
t
PHL
Propagation Delay Time
HIGH-to-LOW Level Output
(Clock LOW)
t
PLH
t
PHL
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Clock to Q or Q
9
12
ns
Clear to Q
8
13
ns
Clear to Q
13.5
16
ns
Preset to Q
8
14
ns
Preset to Q
13.5
17
ns
Preset to Q
C
L
=
15 pF
Min
75
6
Max
C
L
=
50 pF
Min
65
9
Max
MHz
ns
Units
Clear to Q
6
9
ns
Clock to Q or Q
9
14
ns
3
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DM74S74
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A
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4
DM74S74 Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear, and Complementary Outputs
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
5
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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