DM54S280W/883 datasheet, PDF - EEWORLD Datasheet

DM54S280W/883: DescriptionIC S SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, CDFP14, CERAMIC, FP-14, Arithmetic Circuit; Categorylogic logic; File Size182KB，4 Pages; ManufacturerNational Semiconductor（TI ）; Websitehttp://www.ti.com

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DM54S280W/883 Overview

IC S SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, CDFP14, CERAMIC, FP-14, Arithmetic Circuit

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
package instruction	DFP, FL14,.3
Reach Compliance Code	unknown
Other features	ODD/EVEN PARITY GENERATOR
series	S
JESD-30 code	R-GDFP-F14
JESD-609 code	e0
length	9.5885 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	PARITY GENERATOR/CHECKER
Number of digits	9
Number of functions	1
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Output polarity	COMPLEMENTARY
Package body material	CERAMIC, GLASS-SEALED
encapsulated code	DFP
Encapsulate equivalent code	FL14,.3
Package shape	RECTANGULAR
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Maximum supply current (ICC)	105 mA
propagation delay (tpd)	21 ns
Certification status	Not Qualified
Filter level	38535Q/M;38534H;883B
Maximum seat height	2.032 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	TTL
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	FLAT
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	6.35 mm
Base Number Matches	1

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