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NCP1381, NCP1382
Low- Standby High
-
Performance PWM
Controller
Housed in a SO- package, the NCP1381/82 includes everything
-14
needed to build rugged and efficient Quasi-
-Resonant (QR) Switching
Power Supplies. When powered by a front-
-end Power Factor
Correction circuitry, the NCP1381/82 automatically disconnects the
PFC controller in low output loading conditions (with an adjustable
level), thus improving the standby power. This is particularly well
suited for medium to high power offline applications, e.g. notebook
adapters. When the current setpoint falls below a given value, e.g. the
output power demand diminishes, the IC automatically enters the
so-
-called skip cycle mode and provides excellent efficiency at light
loads. Because this occurs at an adjustable low peak current together
with a proprietary Soft-
-Skipt technique, no acoustic noise takes
place. Skip cycle also offers the ability to easily select the maximum
switching frequency at which foldback and standby take place.
The NCP1381/82 also features several efficient protection options
like a) a short-
-circuit / overload detection independent of the auxiliary
voltage b) an auto-
-recovery brown-
-out detection and c) an input to
externally latch the circuit in case of Overvoltage Protection or Over
Temperature Protection.
Features
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HIGH PERFORMANCE QR
CONTROLLER FEATURING PFC
SHUTDOWN
MARKING
DIAGRAM
14
14
1
SOIC-
-14
D SUFFIX
CASE 751A
1
NCP138xG = Specific Device Code
x
= 1 or 2
A
= Assembly Location
WL
= Wafer Lot
Y
= Year
WW
= Work Week
G = Pb--Free Package
NCP138xG
AWLYWW
Current-
-Mode Quasi-
-Resonant Operation
Adjustable Line Over Power Protection
Extremely Low Startup Current of 15
mA
Maximum
Soft-
-Skip Cycle Capability at Adjustable Peak Currents
Plateau Sensing Overvoltage
Brown-
-Out Protection
Maximum t
ON
Limitation
Overpower Protection by current Sense Offset
Internal 5 ms Soft-
-Start Management
Short-
-Circuit Protection Independent from Auxiliary Level
External Latch Input Pin for an OTP Signal
Go- -Standby Signal for the PFC Front Stage
-To-
True Frequency (t
ON
+ t
OFF
) Clamp Circuit
Low and Noiseless, No-
-Load Standby Power
Internal Leading Edge Blanking
+500 mA / -
-800 mA Peak Current Drive Capability
5 V / 10 mA Reference Voltage
These are Pb-
-Free Devices
ADJ_GTS
BO
DMG
Timer
Skip/OVP
FB
CS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
nc
nc
Ref
GTS
V
CC
DRV
GND
ORDERING INFORMATION
Device
NCP1381DR2G
NCP1382DR2G
Package
SOIC--14
(Pb--Free)
SOIC--14
(Pb--Free)
Shipping
†
2500/Tape & Reel
2500/Tape & Reel
Typical Applications
High Power AC/DC Adapters for Notebooks, etc
Offline Battery Chargers
Set--Top Boxes Power Supplies, TV, Monitors, etc
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Semiconductor Components Industries, LLC, 2010
November, 2010 - Rev. 5
-
1
Publication Order Number:
NCP1381/D
NCP1381, NCP1382
TYPICAL APPLICATION EXAMPLE
HV
+
PFC Stage
To PFC’s V
CC
+
OVP
BO
DMG
GTS_ADJ
NCP1381/82
1
2
3
4
5
6
14
13
12
11
10
9
8
+
V
ref
V
out
+
Skip
7
GTS_ADJ
OPP
Figure 1. Typical Application Example
PIN FUNCTION DESCRIPTION
Pin#
1
2
3
4
5
6
7
8
9
10
11
Symbol
GTS_ADJ
BO
DMG
Timer
Skip/OVP
FB
CS
GND
DRV
V
CC
GTS
GTS Level Adjustment
Brown--out
Detects the Zero Voltage
Crossing Point
Fault Timer
Adjust the Skip Level
Feedback Signal
Current Sense Pin
The IC Ground
The Driver Output
V
CC
Input
Directly Powers the PFC
Frontend Stage
Reference Voltage
--
--
Description
An internal comparator senses the signal applied to this pin (typically a portion of
F
B
signal) to detect the standby condition for GTS.
By connecting this pin to a resistive divider, the controller ensures operation at a
safe mains level.
This pin detects the core reset event but also permanently senses the Flyback
plateau, offering a clean OVP detection.
Connecting a capacitor to this pin adjusts the fault timer.
This pin alters the default skip cycle level and offers a mean to latchoff the con-
troller when externally brought above 4 V.
An optocoupler collector pulls this pin down to regulate. When the current set-
point falls below an adjustable level, the controller skips cycles.
This pin cumulates two different functions: the standard sense function plus an
adjustable offset voltage providing the adequate level of Overpower Protection.
--
With a drive capability of
±500
mA/800 mA, the NCP1381 can drive large Q
g
MOSFETs.
The controller accepts voltages up to 20 V and features an UVLO of 10 V typical.
This pin directly powers the PFC controller by routing the PWM V
CC
to the PFC
V
CC
. In standby (defined by GTS_ADJ), fault and BO conditions, this pin is open
and the PFC is no longer supplied.
This pin offers a 5 V reference voltage sourcing up to 10 mA.
Not Connected
Not Connected
12
13
14
Reference
NC
NC
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2
NCP1381, NCP1382
INTERNAL CIRCUIT ARCHITECTURE
5
mA
V
DD
ADJ_GTS
1
ADJ_GTS Section
+
250 mV
--
+
R
ST
Timer
+
--
+
BO
BOComp.
240 mV/
500 mV
V
DD
V
CC
Management
UVLO, Latchoff
+
--
8
ms
No DMG
Timeout
4
ms
Delayed
1 Shot
V
latchDem
+
--
+
DMG
3
+
to
Latch
S
CLK Q
Q
R
Prioritary
Reset
V
DD
1 Shot
shot
t
ON
+ t
OFF
=8
ms
Max F
sw
Clamping
+
--
+
t
ON
> 45
ms?
Fault
/4
Timer
4
SS
Skip
Fault /
Startup
V
TimSS
+
OPP
Offset
I/V 85
mS
--
FB
6
30
mA
V
DD
+
Skip
Section
S
Q
Q
25 k
Latchoff
CS
7
+
+
--
V
latch
Plateau
Sensing
4 V Reset
Soft--Skip
Soft--Start
R
I
P
Flag
GTS
Switches are Kept Closed until NOR
Output Goes Low
SS
Cap
V
DD
8
GND
+
Soft--Start Ended
--
+
+
Timer
--
V
TimFault
V
DD
SS
Cap
9
Drv
UVLO
+
V
ref
BO
GTS
Conf. ?
12
Ref
+
Timer I
P
Flag
BO
2
S
CLK Q
Q
R
DRV
3
ms
1 Shot
DRV
--
+
V
th
DRV
V
DD
DRV
11
GTS
+
--
V
DD
+
+
Timer
10 V
CC
--
I
PFlag
Skip/
OVP
5
LEB
Figure 2. Internal Circuit Architecture
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3
NCP1381, NCP1382
MAXIMUM RATINGS TABLE
Symbol
V
supply
Rating
Maximum Power Supply Voltage on Pin 10 (V
CC
), Pin 9 (DRV), and Pin 11 (GTS)
Maximum Current in Pin 10 (V
CC
)
Maximum Current in Pin 11 (GTS)
Maximum Current in Pin 9 (DRV)
Power Supply Voltage on all Other Pins Except Pin 10 (V
CC
), Pin 9 (DRV), Pin 3 (DMG) and
Pin 11 (GTS)
Maximum Current Into All Other Pins Except Pin 10 (V
CC
), Pin 9 (DRV) and Pin 11 (GTS)
I
dem
R
θJ--A
Maximum Current in Pin 3 (DMG), When 10 V ESD Zener is Activated
Thermal Resistance Junction--to--Air, SO--14
Maximum Junction Temperature
Storage Temperature Range
ESD Capability, Human Body Model per MIL--STD--883, Method 3015 (All Pins Except Ref)
ESD Capability, Human Body Model per MIL--STD--883, Method 3015 (Ref Pin)
ESD Capability, Machine Model
Value
20
30
20
1
--0.3 to 5
10
+3 / --3
150
150
--60 to +150
2
1.8
200
Unit
V
mA
mA
A
V
mA
mA
C/W
C
C
kV
kV
V
TJ
MAX
NOTE: This device contains latchup protection and exceeds 100 mA per JEDEC standard JESD78.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
ELECTRICAL CHARACTERISTICS
(For typical values T
J
= 25C, for min/max values T
J
= 0C to +125C, V
CC
= 12 V unless otherwise noted)
Symbol
SUPPLY SECTION
VCC
ON
VCC
OFF
VCC
latch
VCC
reset
I
startup
I
CC1
I
CC2
I
CC3
T
r
T
f
R
OH
R
OL
I
IB
I
Limit
G
m
T
DELCS
T
LEB
S
Start
S
skip
Turn--on Threshold Level, V
CC
Going Up
Minimum Operating Voltage After Turn--on
V
CC
Decreasing Level at Which the Latchoff Phase Ends
V
CC
Level at Which the Internal Logic Gets Reset
Startup Current (V
CC
< VCC
ON
)
Internal IC Consumption, No Output Load on Pin 9, F
SW
= 60 kHz
Internal IC Consumption, 1 nF Output Load on Pin 9, F
SW
= 60 kHz
Internal IC Consumption, Latchoff Phase
10
10
10
10
10
10
10
10
13
9
--
--
--
--
--
--
15
10
7
4
2
1.4
2.1
1.4
17.9
11
--
--
15
1.8
2.6
--
V
V
V
V
mA
mA
mA
mA
Rating
Pin
Min
Typ
Max
Unit
DRIVE OUTPUT
Output Voltage Rise--Time @ C
L
= 1 nF, 10--90% of Output Signal
Output Voltage Fall--Time @ C
L
= 1 nF, 10--90% of Output Signal
Source Resistance
Sink Resistance
9
9
9
9
--
--
--
--
15
15
9
8
--
--
--
--
ns
ns
Ω
Ω
CURRENT COMPARATOR
Input Bias Current @ 1 V Input Level on Pin 7
Maximum Internal Current Setpoint at V
BO
= 0
Transconductance Amplifier Offsetting CS at V
BO
= 2 V
Propagation Delay from CS Detected to Gate Turned off (Pin 9 Loaded
by 1 nF)
Leading Edge Blanking Duration
Typical Internal Soft--start Period at Startup
Typical Internal Soft--start period when Leaving Skip
7
7
7
7
7
--
--
--
0.75
70
--
300
2.5
100
0.02
0.8
85
90
370
4.0
175
--
0.85
100
--
--
6.0
250
mA
V
mS
ns
ns
ms
ms
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4
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