51
PRELIMINARY
CY7C024V/025V/026V
CY7C0241V/0251V/036V
3.3V 4K/8K/16K x 16/18
Dual-Port Static RAM
Features
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• 4/8/16K x 16 organization (CY7C024V/025V/026V)
• 4/8K x 18 organization (CY7C0241V/0251V)
• 16K x 18 organization (CY7C036V)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 15/25 ns
• Low operating power
—
Active: I
CC
= 115 mA (typical)
— Standby: I
SB3
= 10
µA
(typical)
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 32/36 bits or more using Mas-
ter/Slave chip select when using more than one device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flag for port-to-port communication
• Separate upper-byte and lower-byte control
• Pin select for Master or Slave
• Commercial and industrial temperature ranges
• Available in 100-pin TQFP
• Pin-compatible and functionally equivalent to
IDT70V24, 70V25, and 7V0261.
Logic Block Diagram
R/W
L
UB
L
R/W
R
UB
R
CE
L
LB
L
OE
L
CE
R
LB
R
OE
R
[1]
8/9
8/9
8/9
[1]
I/O
8/9L
–I/O
15/17L
[2]
I/O
0L
–I/O
7/8L
I/O
Control
I/O
Control
8/9
I/O
8/9L
–I/O
15/17R
[2]
I/O
0L
–I/O
7/8R
[3]
12/13/14
A
0L
–A
11/1213L
Address
Decode
12/13/14
True Dual-Ported
RAM Array
Address
Decode
12/13/14
12/13/14
[3]
A
0R
–A
11/12/13R
A
0L
–A
11/12/13L
CE
L
OE
L
R/W
L
SEM
L
[4]
[3]
Interrupt
Semaphore
Arbitration
A
0R
–A
11/12/13R
CE
R
OE
R
R/W
R
SEM
R
[4]
[3]
BUSY
L
INT
L
UB
L
LB
L
Notes:
1. I/O
8
–I/O
15
for x16 devices; I/O
9
–I/O
17
for x18 devices
2. I/O
0
–I/O
7
for x16 devices; I/O
0
–I/O
8
for x18 devices.
M/S
3.
4.
BUSY
R
INT
R
UB
R
LB
R
A
0
–A
11
for 4K devices; A
0
–A
12
for 8K devices; A
0
–A
13
for 16K devices.
BUSY is an output in master mode and an input in slave mode.
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134 •
408-943-2600
November 7, 1997- Revised March 2, 1998
PRELIMINARY
Functional Description
The CY7C024V/025V/026V and CY70241V/0251V/036V are
low-power CMOS 4K, 8K, and 16K x16/18 dual-port static
RAMs. Various arbitration schemes are included on the devic-
es to handle situations when multiple processors access the
same piece of data. Two ports are provided, permitting inde-
pendent, asynchronous access for reads and writes to any
location in memory. The devices can be utilized as standalone
16/18-bit dual-port static RAMs or multiple devices can be
combined in order to function as a 32/36-bit or wider mas-
ter/slave dual-port static RAM. An M/S pin is provided for im-
plementing 32/36-bit or wider memory applications without the
need for separate master and slave devices or additional dis-
crete logic. Application areas include interprocessor/multipro-
CY7C024V/025V/026V
CY7C0241V/0251V/036V
cessor designs, communications status buffering, and du-
al-port video/graphics memory.
Each port has independent control pins: chip enable (CE),
read or write enable (R/W), and output enable (OE). Two flags are
provided on each port (BUSY and INT). BUSY signals that the port
is trying to access the same location currently being accessed by the
other port. The interrupt flag (INT) permits communication between
ports or systems by means of a mail box. The semaphores are used
to pass a flag, or token, from one port to the other to indicate that a
shared resource is in use. The semaphore logic is comprised of eight
shared latches. Only one side can control the latch (semaphore) at
any time. Control of a semaphore indicates that a shared resource is
in use. An automatic power-down feature is controlled independently
on each port by a chip select (CE) pin.
The CY7C024V/025V/026V and CY70241V/0251V/036V are
available in 100-pin Thin Quad Plastic Flatpacks (TQFP).
Pin Configurations
100-Pin TQFP
Top View
OE
L
V
CC
R/W
L
SEM
L
CE
L
UB
L
LB
L
NC
[5]
A
11L
A
10L
I/O
4L
I/O
3L
I/O
2L
GND
I/O
9L
I/O
8L
I/O
7L
I/O
6L
I/O
5L
I/O
1L
I/O
0L
A
9L
A
8L
A
7L
A
6L
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
NC
NC
NC
NC
I/O
10L
I/O
11L
I/O
12L
I/O
13L
GND
I/O
14L
I/O
15L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
NC
NC
NC
NC
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
NC
NC
NC
NC
CY7C024V (4K x 16)
CY7C025V (8K x 16)
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
GND
I/O
15R
Œ
R
I/O
7R
I/O
8R
I/O
9R
I/O
10R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
R/W
R
GND
SEM
R
CE
R
UB
R
LB
R
NC
[6]
A
11R
A
10R
A
9R
A
8R
Notes:
5. A
12L
on the CY7C025.
6. A
12R
on the CY7C025.
2
A
7R
A
6R
A
5R
PRELIMINARY
Pin Configurations
(continued)
100-Pin TQFP
I/O
10L
I/O
9L
I/O
7L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
GND
I/O
1L
I/O
0L
CY7C024V/025V/026V
CY7C0241V/0251V/036V
Top View
UB
L
LB
L
NC
[7]
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
NC
NC
I/O
8L
I/O
17L
I/O
11L
I/O
12L
I/O
13L
I/O
14L
GND
I/O
15L
I/O
16L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
I/O
8R
I/O
17R
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
NC
NC
NC
NC
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
NC
NC
NC
NC
CY7C0241V (4K x 18)
CY7C0251V (8K x 18)
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
OE
L
V
CC
R/W
L
SEM
L
CE
L
I/O
10R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
I/O
15R
GND
I/O
16R
OE
R
R/W
R
GND
SEM
R
CE
R
UB
R
LB
R
I/O
7R
I/O
9R
NC
[8]
A
11R
A
10R
A
9R
A
8R
CEL
UBL
LBL
A113L
VCC
R/WL
SEML
I/O9L
I/O8L
I/O7L
I/O6L
I/O5L
I/O4L
I/O3L
I/O2L
GND
I/O1L
I/O0L
OEL
A12L
A11L
A10L
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
NC
NC
NC
NC
I/O10L
I/O11L
I/O12L
I/O13L
GND
I/O14L
I/O15L
VCC
GND
I/O0R
I/O1R
I/O2R
VCC
I/O3R
I/O4R
I/O5R
I/O6R
NC
NC
NC
NC
75
1
2
74
73
3
72
4
71
5
6
70
69
7
68
8
67
9
10
66
65
11
64
12
63
13
62
14
61
15
60
16
17
59
18
58
19
57
20
56
21
55
22
54
23
53
24
52
25
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
NC
NC
A6L
A5L
A4L
A3L
A2L
A1L
A0L
INTL
BUSYL
GND
M/S
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
A5R
NC
NC
NC
CY7C026V (16K x 16)
I/O7R
I/O8R
I/O9R
I/O10R
I/O11R
I/O12R
I/O13R
I/O14R
GND
I/O15R
OER
R/WR
GND
SEMR
CER
UBR
LBR
A13R
A12R
A11R
A10R
A9R
Notes:
7. A
12L
on the CY7C0251.
8. A
12R
on the CY7C0251.
3
A8R
A7R
A6R
A9L
A8L
A7L
A
7R
A
6R
A
5R
PRELIMINARY
Pin Configurations
(continued)
100-Pin TQFP
Top View
I/O
10L
I/O
9L
I/O
7L
I/O
6L
I/O
5L
OE
L
V
CC
R/W
L
SEM
L
CE
L
I/O
4L
I/O
3L
I/O
2L
GND
I/O
1L
I/O
0L
UB
L
LB
L
A
12L
A
11L
A
10L
CY7C024V/025V/026V
CY7C0241V/0251V/036V
A
9L
A
8L
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
NC
NC
I/O
8L
I/O
17L
I/O
11L
I/O
12L
I/O
13L
I/O
14L
GND
I/O
15L
I/O
16L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
I/O
8R
I/O
17R
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
NC
A
13L
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
13R
NC
NC
NC
CY7C036V (16K x 18)
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
I/O
7R
I/O
9R
I/O
10R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
I/O
15R
GND
I/O
16R
OE
R
R/W
R
GND
SEM
R
CE
R
UB
R
LB
R
A
12R
A
11R
A
10R
A
9R
A
8R
Selection Guide
CY7C024V/025V/026V
CY7C0241V/0251V/036V
-15
Maximum Access Time (ns)
Typical Operating Current (mA)
Typical Standby Current for I
SB1
(mA) (Both ports TTL level)
Typical Standby Current for I
SB3
(µA) (Both ports CMOS level)
15
125
35
10
µA
CY7C024V/025V/026V
CY7C0241V/0251V/036V
-25
25
115
30
10
µA
4
A
7R
A
6R
A
5R
A
7L
A
6L
PRELIMINARY
Pin Definitions
Left Port
CE
L
R/W
L
OE
L
A
0L
–A
13L
I/O
0L
–I/O
17L
SEM
L
UB
L
LB
L
INT
L
BUSY
L
M/S
V
CC
GND
NC
CE
R
R/W
R
OE
R
A
0R
–A
13R
I/O
0R
–I/O
17R
SEM
R
UB
R
LB
R
INT
R
BUSY
R
Right Port
Chip Enable
Read/Write Enable
Output Enable
CY7C024V/025V/026V
CY7C0241V/0251V/036V
Description
Address (A
0
–A
11
for 4K devices; A
0
–A
12
for 8K devices; A
0
–A
13
for 16K)
Data Bus Input/Output
Semaphore Enable
Upper Byte Select (I/O
8
–I/O
15
for x16 devices; I/O
9
–I/O
17
for x18 devices)
Lower Byte Select (I/O
0
–I/O
7
for x16 devices; I/O
0
–I/O
8
for x18 devices)
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
No Connect
DC Input Voltage
[9]
.................................. –0.5V to V
CC
+0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... >2001V
Latch-Up Current.................................................... >200 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65
°
C to +150
°
C
Ambient Temperature with
Power Applied .............................................–55
°
C to +125
°
C
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
DC Voltage Applied to
Outputs in High Z State ...........................–0.5V to V
CC
+0.5V
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0
°
C to +70
°
C
–40
°
C to +85
°
C
V
CC
3.3V
±
300 mV
3.3V
±
300 mV
Note:
9. Pulse width < 20 ns.
5
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